Commit 25075146 authored by Arnd Bergmann's avatar Arnd Bergmann
Browse files

Merge tag 'qcom-arm64-for-4.15' of... 

Merge tag 'qcom-arm64-for-4.15' of git://git.kernel.org/pub/scm/linux/kernel/git/agross/linux into next/soc

Pull "Qualcomm ARM64 Updates for v4.15" from Andy Gross:

* Add PCIE support to relevant MSM8996 based boards
* Add RPM clock controller node on MSM8996
* Add dload address on MSM8916 and MSM8996
* Add MBHC button support on APQ8016 SBC
* Add RTMFS specific compatible for rmtfs memory node
* Fixups for MSM8916 GPIO line names and MDP address length

* tag 'qcom-arm64-for-4.15' of git://git.kernel.org/pub/scm/linux/kernel/git/agross/linux:
  arm64: dts: msm8916: Mark rmtfs node as qcom, rmtfs-mem compatible
  arm64: dts: msm8996: Add the rpm clock controller node
  arm64: dts: qcom: sbc: Name GPIO lines
  arm64: dts: qcom: msm8916: Shrink mdp address length for msm8916
  arm64: dts: apq8016-sbc: add mbhc buttons support
  arm64: dts: qcom: Specify dload address for msm8916 and msm8996
  arm64: dts: apq8096-db820c: never disable regulator on LS expansion
  arm64: dts: apq8096-db820c: Enable on board 3 pcie root complex
  arm64: dts: qcom: msm8996: add support to pcie
parents c94c8139 8cd00d5a

arch/arm64/boot/dts/qcom/apq8016-sbc.dtsi

+171 −0
Original line number Diff line number Diff line
@@ -19,6 +19,30 @@ 
#include <dt-bindings/input/input.h>

#include <dt-bindings/sound/apq8016-lpass.h>



/*

 * GPIO name legend: proper name = the GPIO line is used as GPIO

 *         NC = not connected (pin out but not routed from the chip to

 *              anything the board)

 *         "[PER]" = pin is muxed for [peripheral] (not GPIO)

 *         LSEC = Low Speed External Connector

 *         HSEC = High Speed External Connector

 *

 * Line names are taken from the schematic "DragonBoard410c"

 * dated monday, august 31, 2015. Page 5 in particular.

 *

 * For the lines routed to the external connectors the

 * lines are named after the 96Boards CE Specification 1.0,

 * Appendix "Expansion Connector Signal Description".

 *

 * When the 96Board naming of a line and the schematic name of

 * the same line are in conflict, the 96Board specification

 * takes precedence, which means that the external UART on the

 * LSEC is named UART0 while the schematic and SoC names this

 * UART3. This is only for the informational lines i.e. "[FOO]",

 * the GPIO named lines "GPIO-A" thru "GPIO-L" are the only

 * ones actually used for GPIO.

 */



/ {

	aliases {

		serial0 = &blsp1_uart2;
@@ -47,6 +71,132 @@ 
	};



	soc {

		pinctrl@1000000 {

			gpio-line-names =

				"[UART0_TX]", /* GPIO_0, LSEC pin 5 */

				"[UART0_RX]", /* GPIO_1, LSEC pin 7 */

				"[UART0_CTS_N]", /* GPIO_2, LSEC pin 3 */

				"[UART0_RTS_N]", /* GPIO_3, LSEC pin 9 */

				"[UART1_TX]", /* GPIO_4, LSEC pin 11 */

				"[UART1_RX]", /* GPIO_5, LSEC pin 13 */

				"[I2C0_SDA]", /* GPIO_8, LSEC pin 17 */

				"[I2C0_SCL]", /* GPIO_7, LSEC pin 15 */

				"[SPI1_DOUT]", /* SPI1_MOSI, HSEC pin 1 */

				"[SPI1_DIN]", /* SPI1_MISO, HSEC pin 11 */

				"[SPI1_CS]", /* SPI1_CS_N, HSEC pin 7 */

				"[SPI1_SCLK]", /* SPI1_CLK, HSEC pin 9 */

				"GPIO-B", /* LS_EXP_GPIO_B, LSEC pin 24 */

				"GPIO-C", /* LS_EXP_GPIO_C, LSEC pin 25 */

				"[I2C3_SDA]", /* HSEC pin 38 */

				"[I2C3_SCL]", /* HSEC pin 36 */

				"[SPI0_MOSI]", /* LSEC pin 14 */

				"[SPI0_MISO]", /* LSEC pin 10 */

				"[SPI0_CS_N]", /* LSEC pin 12 */

				"[SPI0_CLK]", /* LSEC pin 8 */

				"HDMI_HPD_N", /* GPIO 20 */

				"USR_LED_1_CTRL",

				"[I2C1_SDA]", /* GPIO_22, LSEC pin 21 */

				"[I2C1_SCL]", /* GPIO_23, LSEC pin 19 */

				"GPIO-G", /* LS_EXP_GPIO_G, LSEC pin 29 */

				"GPIO-H", /* LS_EXP_GPIO_H, LSEC pin 30 */

				"[CSI0_MCLK]", /* HSEC pin 15 */

				"[CSI1_MCLK]", /* HSEC pin 17 */

				"GPIO-K", /* LS_EXP_GPIO_K, LSEC pin 33 */

				"[I2C2_SDA]", /* HSEC pin 34 */

				"[I2C2_SCL]", /* HSEC pin 32 */

				"DSI2HDMI_INT_N",

				"DSI_SW_SEL_APQ",

				"GPIO-L", /* LS_EXP_GPIO_L, LSEC pin 34 */

				"GPIO-J", /* LS_EXP_GPIO_J, LSEC pin 32 */

				"GPIO-I", /* LS_EXP_GPIO_I, LSEC pin 31 */

				"GPIO-A", /* LS_EXP_GPIO_A, LSEC pin 23 */

				"FORCED_USB_BOOT",

				"SD_CARD_DET_N",

				"[WCSS_BT_SSBI]",

				"[WCSS_WLAN_DATA_2]", /* GPIO 40 */

				"[WCSS_WLAN_DATA_1]",

				"[WCSS_WLAN_DATA_0]",

				"[WCSS_WLAN_SET]",

				"[WCSS_WLAN_CLK]",

				"[WCSS_FM_SSBI]",

				"[WCSS_FM_SDI]",

				"[WCSS_BT_DAT_CTL]",

				"[WCSS_BT_DAT_STB]",

				"NC",

				"NC", /* GPIO 50 */

				"NC",

				"NC",

				"NC",

				"NC",

				"NC",

				"NC",

				"NC",

				"NC",

				"NC",

				"NC", /* GPIO 60 */

				"NC",

				"NC",

				"[CDC_PDM0_CLK]",

				"[CDC_PDM0_SYNC]",

				"[CDC_PDM0_TX0]",

				"[CDC_PDM0_RX0]",

				"[CDC_PDM0_RX1]",

				"[CDC_PDM0_RX2]",

				"GPIO-D", /* LS_EXP_GPIO_D, LSEC pin 26 */

				"NC", /* GPIO 70 */

				"NC",

				"NC",

				"NC",

				"NC", /* GPIO 74 */

				"NC",

				"NC",

				"NC",

				"NC",

				"NC",

				"BOOT_CONFIG_0", /* GPIO 80 */

				"BOOT_CONFIG_1",

				"BOOT_CONFIG_2",

				"BOOT_CONFIG_3",

				"NC",

				"NC",

				"BOOT_CONFIG_5",

				"NC",

				"NC",

				"NC",

				"NC", /* GPIO 90 */

				"NC",

				"NC",

				"NC",

				"NC",

				"NC",

				"NC",

				"NC",

				"NC",

				"NC",

				"NC", /* GPIO 100 */

				"NC",

				"NC",

				"NC",

				"SSBI_GPS",

				"NC",

				"NC",

				"KEY_VOLP_N",

				"NC",

				"NC",

				"[LS_EXP_MI2S_WS]", /* GPIO 110 */

				"NC",

				"NC",

				"[LS_EXP_MI2S_SCK]",

				"[LS_EXP_MI2S_DATA0]",

				"GPIO-E", /* LS_EXP_GPIO_E, LSEC pin 27 */

				"NC",

				"[DSI2HDMI_MI2S_WS]",

				"[DSI2HDMI_MI2S_SCK]",

				"[DSI2HDMI_MI2S_DATA0]",

				"USR_LED_2_CTRL", /* GPIO 120 */

				"SB_HS_ID";

		};



		dma@7884000 {

			status = "okay";

		};
@@ -329,6 +479,25 @@ 
                        };

                };



		spmi@200f000 {

			pm8916@0 {

				gpios@c000 {

					gpio-line-names =

						"USR_LED_3_CTRL",

						"USR_LED_4_CTRL",

						"USB_HUB_RESET_N_PM",

						"USB_SW_SEL_PM";

				};

				mpps@a000 {

					gpio-line-names =

						"VDD_PX_BIAS",

						"WLAN_LED_CTRL",

						"BT_LED_CTRL",

						"GPIO-F"; /* LS_EXP_GPIO_F, LSEC pin 28 */

				};

			};

		};



		wcnss@a21b000 {

			status = "okay";

		};
@@ -379,6 +548,8 @@ 
        status = "okay";

        clocks = <&gcc GCC_CODEC_DIGCODEC_CLK>;

        clock-names = "mclk";

	qcom,mbhc-vthreshold-low = <75 150 237 450 500>;

	qcom,mbhc-vthreshold-high = <75 150 237 450 500>;

};



&smd_rpm_regulators {

arch/arm64/boot/dts/qcom/apq8096-db820c.dtsi

+22 −0
Original line number Diff line number Diff line
@@ -138,6 +138,22 @@ 
			pinctrl-names = "default";

			pinctrl-0 = <&usb2_vbus_det_gpio>;

		};



		agnoc@0 {

			qcom,pcie@00600000 {

				perst-gpio = <&msmgpio 35 GPIO_ACTIVE_LOW>;

			};



			qcom,pcie@00608000 {

				status = "okay";

				perst-gpio = <&msmgpio 130 GPIO_ACTIVE_LOW>;

			};



			qcom,pcie@00610000 {

				status = "okay";

				perst-gpio = <&msmgpio 114 GPIO_ACTIVE_LOW>;

			};

		};

	};
@@ -173,9 +189,15 @@ 
					regulator-min-microvolt = <1300000>;

					regulator-max-microvolt = <1300000>;

				};



				/**

				 * 1.8v required on LS expansion

				 * for mezzanine boards

				 */

				s4 {

					regulator-min-microvolt = <1800000>;

					regulator-max-microvolt = <1800000>;

					regulator-always-on;

				};

				s5 {

					regulator-min-microvolt = <2150000>;

arch/arm64/boot/dts/qcom/msm8916.dtsi

+6 −1
Original line number Diff line number Diff line
@@ -69,8 +69,11 @@ 
		};



		rmtfs@86700000 {

			compatible = "qcom,rmtfs-mem";

			reg = <0x0 0x86700000 0x0 0xe0000>;

			no-map;



			qcom,client-id = <1>;

		};



		rfsa@867e00000 {
@@ -257,6 +260,8 @@ 
			clocks = <&gcc GCC_CRYPTO_CLK>, <&gcc GCC_CRYPTO_AXI_CLK>, <&gcc GCC_CRYPTO_AHB_CLK>;

			clock-names = "core", "bus", "iface";

			#reset-cells = <1>;



			qcom,dload-mode = <&tcsr 0x6100>;

		};

	};
@@ -814,7 +819,7 @@ 


			mdp: mdp@1a01000 {

				compatible = "qcom,mdp5";

				reg = <0x1a01000 0x90000>;

				reg = <0x1a01000 0x89000>;

				reg-names = "mdp_phys";



				interrupt-parent = <&mdss>;

arch/arm64/boot/dts/qcom/msm8996-pins.dtsi

+195 −0
Original line number Diff line number Diff line
@@ -300,4 +300,199 @@ 
			drive-strength = <2>;	/* 2 MA */

		};

	};



	pcie0_clkreq_default: pcie0_clkreq_default {

		mux {

			pins = "gpio36";

			function = "pci_e0";

		};



		config {

			pins = "gpio36";

			drive-strength = <2>;

			bias-pull-up;

		};

	};



	pcie0_perst_default: pcie0_perst_default {

		mux {

			pins = "gpio35";

			function = "gpio";

		};



		config {

			pins = "gpio35";

			drive-strength = <2>;

			bias-pull-down;

		};

	};



	pcie0_wake_default: pcie0_wake_default {

		mux {

			pins = "gpio37";

			function = "gpio";

		};



		config {

			pins = "gpio37";

			drive-strength = <2>;

			bias-pull-up;

		};

	};



	pcie0_clkreq_sleep: pcie0_clkreq_sleep {

		mux {

			pins = "gpio36";

			function = "gpio";

		};



		config {

			pins = "gpio36";

			drive-strength = <2>;

			bias-disable;

		};

	};



	pcie0_wake_sleep: pcie0_wake_sleep {

		mux {

			pins = "gpio37";

			function = "gpio";

		};



		config {

			pins = "gpio37";

			drive-strength = <2>;

			bias-disable;

		};

	};



	pcie1_clkreq_default: pcie1_clkreq_default {

		mux {

			pins = "gpio131";

			function = "pci_e1";

		};



		config {

			pins = "gpio131";

			drive-strength = <2>;

			bias-pull-up;

		};

	};



	pcie1_perst_default: pcie1_perst_default {

		mux {

			pins = "gpio130";

			function = "gpio";

		};



		config {

			pins = "gpio130";

			drive-strength = <2>;

			bias-pull-down;

		};

	};



	pcie1_wake_default: pcie1_wake_default {

		mux {

			pins = "gpio132";

			function = "gpio";

		};



		config {

			pins = "gpio132";

			drive-strength = <2>;

			bias-pull-down;

		};

	};



	pcie1_clkreq_sleep: pcie1_clkreq_sleep {

		mux {

			pins = "gpio131";

			function = "gpio";

		};



		config {

			pins = "gpio131";

			drive-strength = <2>;

			bias-disable;

		};

	};



	pcie1_wake_sleep: pcie1_wake_sleep {

		mux {

			pins = "gpio132";

			function = "gpio";

		};



		config {

			pins = "gpio132";

			drive-strength = <2>;

			bias-disable;

		};

	};



	pcie2_clkreq_default: pcie2_clkreq_default {

		mux {

			pins = "gpio115";

			function = "pci_e2";

		};



		config {

			pins = "gpio115";

			drive-strength = <2>;

			bias-pull-up;

		};

	};



	pcie2_perst_default: pcie2_perst_default {

		mux {

			pins = "gpio114";

			function = "gpio";

		};



		config {

			pins = "gpio114";

			drive-strength = <2>;

			bias-pull-down;

		};

	};



	pcie2_wake_default: pcie2_wake_default {

		mux {

			pins = "gpio116";

			function = "gpio";

		};



		config {

			pins = "gpio116";

			drive-strength = <2>;

			bias-pull-down;

		};

	};



	pcie2_clkreq_sleep: pcie2_clkreq_sleep {

		mux {

			pins = "gpio115";

			function = "gpio";

		};



		config {

			pins = "gpio115";

			drive-strength = <2>;

			bias-disable;

		};

	};



	pcie2_wake_sleep: pcie2_wake_sleep {

		mux {

			pins = "gpio116";

			function = "gpio";

		};



		config {

			pins = "gpio116";

			drive-strength = <2>;

			bias-disable;

		};

	};

};

arch/arm64/boot/dts/qcom/msm8996.dtsi

+179 −0
Original line number Diff line number Diff line
@@ -13,6 +13,7 @@ 
#include <dt-bindings/interrupt-controller/arm-gic.h>

#include <dt-bindings/clock/qcom,gcc-msm8996.h>

#include <dt-bindings/clock/qcom,mmcc-msm8996.h>

#include <dt-bindings/clock/qcom,rpmcc.h>



/ {

	model = "Qualcomm Technologies, Inc. MSM8996";
@@ -261,6 +262,8 @@ 
	firmware {

		scm {

			compatible = "qcom,scm-msm8996";



			qcom,dload-mode = <&tcsr 0x13000>;

		};

	};
@@ -289,6 +292,11 @@ 
			compatible = "qcom,rpm-msm8996";

			qcom,glink-channels = "rpm_requests";



			rpmcc: qcom,rpmcc {

				compatible = "qcom,rpmcc-msm8996";

				#clock-cells = <1>;

			};



			pm8994-regulators {

				compatible = "qcom,rpm-pm8994-regulators";
@@ -358,6 +366,11 @@ 
			reg = <0x740000 0x20000>;

		};



		tcsr: syscon@7a0000 {

			compatible = "qcom,tcsr-msm8996", "syscon";

			reg = <0x7a0000 0x18000>;

		};



		intc: interrupt-controller@9bc0000 {

			compatible = "arm,gic-v3";

			#interrupt-cells = <3>;
@@ -819,6 +832,172 @@ 
				phy-names = "usb2-phy", "usb3-phy";

			};

		};



		agnoc@0 {

			power-domains = <&gcc AGGRE0_NOC_GDSC>;

			compatible = "simple-pm-bus";

			#address-cells = <1>;

			#size-cells = <1>;

			ranges;



			pcie0: qcom,pcie@00600000 {

				compatible = "qcom,pcie-msm8996", "snps,dw-pcie";

				status = "disabled";

				power-domains = <&gcc PCIE0_GDSC>;

				bus-range = <0x00 0xff>;

				num-lanes = <1>;



				reg = <0x00600000 0x2000>,

				      <0x0c000000 0xf1d>,

				      <0x0c000f20 0xa8>,

				      <0x0c100000 0x100000>;

				reg-names = "parf", "dbi", "elbi","config";



				phys = <&pciephy_0>;

				phy-names = "pciephy";



				#address-cells = <3>;

				#size-cells = <2>;

				ranges = <0x01000000 0x0 0x0c200000 0x0c200000 0x0 0x100000>,

					<0x02000000 0x0 0x0c300000 0x0c300000 0x0 0xd00000>;



				interrupts = <GIC_SPI 405 IRQ_TYPE_NONE>;

				interrupt-names = "msi";

				#interrupt-cells = <1>;

				interrupt-map-mask = <0 0 0 0x7>;

				interrupt-map = <0 0 0 1 &intc 0 244 IRQ_TYPE_LEVEL_HIGH>, /* int_a */

						<0 0 0 2 &intc 0 245 IRQ_TYPE_LEVEL_HIGH>, /* int_b */

						<0 0 0 3 &intc 0 247 IRQ_TYPE_LEVEL_HIGH>, /* int_c */

						<0 0 0 4 &intc 0 248 IRQ_TYPE_LEVEL_HIGH>; /* int_d */



				pinctrl-names = "default", "sleep";

				pinctrl-0 = <&pcie0_clkreq_default &pcie0_perst_default &pcie0_wake_default>;

				pinctrl-1 = <&pcie0_clkreq_sleep &pcie0_perst_default &pcie0_wake_sleep>;





				vdda-supply = <&pm8994_l28>;



				linux,pci-domain = <0>;



				clocks = <&gcc GCC_PCIE_0_PIPE_CLK>,

					<&gcc GCC_PCIE_0_AUX_CLK>,

					<&gcc GCC_PCIE_0_CFG_AHB_CLK>,

					<&gcc GCC_PCIE_0_MSTR_AXI_CLK>,

					<&gcc GCC_PCIE_0_SLV_AXI_CLK>;



				clock-names =  "pipe",

						"aux",

						"cfg",

						"bus_master",

						"bus_slave";



			};



			pcie1: qcom,pcie@00608000 {

				compatible = "qcom,pcie-msm8996", "snps,dw-pcie";

				power-domains = <&gcc PCIE1_GDSC>;

				bus-range = <0x00 0xff>;

				num-lanes = <1>;



				status  = "disabled";



				reg = <0x00608000 0x2000>,

				      <0x0d000000 0xf1d>,

				      <0x0d000f20 0xa8>,

				      <0x0d100000 0x100000>;



				reg-names = "parf", "dbi", "elbi","config";



				phys = <&pciephy_1>;

				phy-names = "pciephy";



				#address-cells = <3>;

				#size-cells = <2>;

				ranges = <0x01000000 0x0 0x0d200000 0x0d200000 0x0 0x100000>,

					<0x02000000 0x0 0x0d300000 0x0d300000 0x0 0xd00000>;



				interrupts = <GIC_SPI 413 IRQ_TYPE_NONE>;

				interrupt-names = "msi";

				#interrupt-cells = <1>;

				interrupt-map-mask = <0 0 0 0x7>;

				interrupt-map = <0 0 0 1 &intc 0 272 IRQ_TYPE_LEVEL_HIGH>, /* int_a */

						<0 0 0 2 &intc 0 273 IRQ_TYPE_LEVEL_HIGH>, /* int_b */

						<0 0 0 3 &intc 0 274 IRQ_TYPE_LEVEL_HIGH>, /* int_c */

						<0 0 0 4 &intc 0 275 IRQ_TYPE_LEVEL_HIGH>; /* int_d */



				pinctrl-names = "default", "sleep";

				pinctrl-0 = <&pcie1_clkreq_default &pcie1_perst_default &pcie1_wake_default>;

				pinctrl-1 = <&pcie1_clkreq_sleep &pcie1_perst_default &pcie1_wake_sleep>;





				vdda-supply = <&pm8994_l28>;

				linux,pci-domain = <1>;



				clocks = <&gcc GCC_PCIE_1_PIPE_CLK>,

					<&gcc GCC_PCIE_1_AUX_CLK>,

					<&gcc GCC_PCIE_1_CFG_AHB_CLK>,

					<&gcc GCC_PCIE_1_MSTR_AXI_CLK>,

					<&gcc GCC_PCIE_1_SLV_AXI_CLK>;



				clock-names =  "pipe",

						"aux",

						"cfg",

						"bus_master",

						"bus_slave";

			};



			pcie2: qcom,pcie@00610000 {

				compatible = "qcom,pcie-msm8996", "snps,dw-pcie";

				power-domains = <&gcc PCIE2_GDSC>;

				bus-range = <0x00 0xff>;

				num-lanes = <1>;

				status = "disabled";

				reg = <0x00610000 0x2000>,

				      <0x0e000000 0xf1d>,

				      <0x0e000f20 0xa8>,

				      <0x0e100000 0x100000>;



				reg-names = "parf", "dbi", "elbi","config";



				phys = <&pciephy_2>;

				phy-names = "pciephy";



				#address-cells = <3>;

				#size-cells = <2>;

				ranges = <0x01000000 0x0 0x0e200000 0x0e200000 0x0 0x100000>,

					<0x02000000 0x0 0x0e300000 0x0e300000 0x0 0x1d00000>;



				device_type = "pci";



				interrupts = <GIC_SPI 421 IRQ_TYPE_NONE>;

				interrupt-names = "msi";

				#interrupt-cells = <1>;

				interrupt-map-mask = <0 0 0 0x7>;

				interrupt-map = <0 0 0 1 &intc 0 142 IRQ_TYPE_LEVEL_HIGH>, /* int_a */

						<0 0 0 2 &intc 0 143 IRQ_TYPE_LEVEL_HIGH>, /* int_b */

						<0 0 0 3 &intc 0 144 IRQ_TYPE_LEVEL_HIGH>, /* int_c */

						<0 0 0 4 &intc 0 145 IRQ_TYPE_LEVEL_HIGH>; /* int_d */



				pinctrl-names = "default", "sleep";

				pinctrl-0 = <&pcie2_clkreq_default &pcie2_perst_default &pcie2_wake_default>;

				pinctrl-1 = <&pcie2_clkreq_sleep &pcie2_perst_default &pcie2_wake_sleep >;



				vdda-supply = <&pm8994_l28>;



				linux,pci-domain = <2>;

				clocks = <&gcc GCC_PCIE_2_PIPE_CLK>,

					<&gcc GCC_PCIE_2_AUX_CLK>,

					<&gcc GCC_PCIE_2_CFG_AHB_CLK>,

					<&gcc GCC_PCIE_2_MSTR_AXI_CLK>,

					<&gcc GCC_PCIE_2_SLV_AXI_CLK>;



				clock-names =  "pipe",

						"aux",

						"cfg",

						"bus_master",

						"bus_slave";

			};

		};

	};



	adsp-pil {

CRA Git | Maintained and supported by SUSTech CRA and CCSE