Commit 24f7dd7e authored by Dmytro Laktyushkin's avatar Dmytro Laktyushkin Committed by Alex Deucher
Browse files

drm/amd/display: move pplib/smu notification to dccg block 



This is done to clear up the clock programming sequence
since the only time we need to notify pplib is after
clock update.

This also renames the clk block to dccg, at the moment
this block contains both clock management and dccg
functionality.

Signed-off-by: default avatarDmytro Laktyushkin <Dmytro.Laktyushkin@amd.com>
Reviewed-by: default avatarTony Cheng <Tony.Cheng@amd.com>
Acked-by: default avatarBhawanpreet Lakha <Bhawanpreet.Lakha@amd.com>
Signed-off-by: default avatarAlex Deucher <alexander.deucher@amd.com>
parent 72942b3d

drivers/gpu/drm/amd/display/dc/core/dc.c

+0 −8
Original line number Diff line number Diff line
@@ -957,8 +957,6 @@ static enum dc_status dc_commit_state_no_check(struct dc *dc, struct dc_state *c 
	}



	/* Program hardware */

	dc->hwss.ready_shared_resources(dc, context);



	for (i = 0; i < dc->res_pool->pipe_count; i++) {

		pipe = &context->res_ctx.pipe_ctx[i];

		dc->hwss.wait_for_mpcc_disconnect(dc, dc->res_pool, pipe);
@@ -1020,8 +1018,6 @@ static enum dc_status dc_commit_state_no_check(struct dc *dc, struct dc_state *c 


	dc_retain_state(dc->current_state);



	dc->hwss.optimize_shared_resources(dc);



	return result;

}
@@ -1448,12 +1444,8 @@ static void commit_planes_do_stream_update(struct dc *dc, 
			if (stream_update->dpms_off) {

				if (*stream_update->dpms_off) {

					core_link_disable_stream(pipe_ctx, KEEP_ACQUIRED_RESOURCE);

					dc->hwss.pplib_apply_display_requirements(

						dc, dc->current_state);

					notify_display_count_to_smu(dc, dc->current_state);

				} else {

					dc->hwss.pplib_apply_display_requirements(

						dc, dc->current_state);

					notify_display_count_to_smu(dc, dc->current_state);

					core_link_enable_stream(dc->current_state, pipe_ctx);

				}

drivers/gpu/drm/amd/display/dc/core/dc_link.c

+3 −18
Original line number Diff line number Diff line
@@ -1357,28 +1357,13 @@ static enum dc_status enable_link_dp( 
	struct dc_link *link = stream->sink->link;

	struct dc_link_settings link_settings = {0};

	enum dp_panel_mode panel_mode;

	enum dc_link_rate max_link_rate = LINK_RATE_HIGH2;



	/* get link settings for video mode timing */

	decide_link_settings(stream, &link_settings);



	/* raise clock state for HBR3 if required. Confirmed with HW DCE/DPCS

	 * logic for HBR3 still needs Nominal (0.8V) on VDDC rail

	 */

	if (link->link_enc->features.flags.bits.IS_HBR3_CAPABLE)

		max_link_rate = LINK_RATE_HIGH3;



	if (link_settings.link_rate == max_link_rate) {

		struct dc_clocks clocks = state->bw.dcn.clk;



		/* dce/dcn compat, do not update dispclk */

		clocks.dispclk_khz = 0;

		/* 27mhz = 27000000hz= 27000khz */

		clocks.phyclk_khz = link_settings.link_rate * 27000;



		state->dis_clk->funcs->update_clocks(

				state->dis_clk, &clocks, false);

	}

	pipe_ctx->stream_res.pix_clk_params.requested_sym_clk =

			link_settings.link_rate * LINK_RATE_REF_FREQ_IN_KHZ;

	state->dccg->funcs->update_clocks(state->dccg, state, false);



	dp_enable_link_phy(

		link,

drivers/gpu/drm/amd/display/dc/core/dc_resource.c

+1 −1
Original line number Diff line number Diff line
@@ -2071,7 +2071,7 @@ void dc_resource_state_construct( 
		const struct dc *dc,

		struct dc_state *dst_ctx)

{

	dst_ctx->dis_clk = dc->res_pool->dccg;

	dst_ctx->dccg = dc->res_pool->dccg;

}



enum dc_status dc_validate_global_state(

drivers/gpu/drm/amd/display/dc/dc.h

+0 −5
Original line number Diff line number Diff line
@@ -304,11 +304,6 @@ struct dc { 
	struct hw_sequencer_funcs hwss;

	struct dce_hwseq *hwseq;



	/* temp store of dm_pp_display_configuration

	 * to compare to see if display config changed

	 */

	struct dm_pp_display_configuration prev_display_config;



	bool optimized_required;



	/* FBC compressor */

drivers/gpu/drm/amd/display/dc/dce/dce_clocks.c

+426 −233

File changed.

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