Commit 24ea098b authored by Tejas Upadhyay's avatar Tejas Upadhyay Committed by Maarten Lankhorst
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drm/i915/jsl: Split EHL/JSL platform info and PCI ids 



Recently we came across requirement to identify EHL and JSL
platform to program them differently. Thus Split the basic
platform definition, macros, and PCI IDs to differentiate
between EHL and JSL platforms. Also, IS_ELKHARTLAKE is replaced
with IS_JSL_EHL everywhere.

Changes since V1 :
	- Rebased to avoid merge conflicts
	- Added missed check for jasperlake in intel_uc_fw.c

Cc : Matt Roper <matthew.d.roper@intel.com>
Cc : Ville Syrjälä <ville.syrjala@linux.intel.com>
Signed-off-by: default avatarTejas Upadhyay <tejaskumarx.surendrakumar.upadhyay@intel.com>
Reviewed-by: default avatarMatt Roper <matthew.d.roper@intel.com>
Signed-off-by: default avatarMaarten Lankhorst <maarten.lankhorst@linux.intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20201013192948.63470-1-tejaskumarx.surendrakumar.upadhyay@intel.com
parent 055f8458

drivers/gpu/drm/i915/display/icl_dsi.c

+2 −2
Original line number Diff line number Diff line
@@ -455,7 +455,7 @@ static void gen11_dsi_config_phy_lanes_sequence(struct intel_encoder *encoder) 
		intel_de_write(dev_priv, ICL_PORT_TX_DW2_GRP(phy), tmp);



		/* For EHL, TGL, set latency optimization for PCS_DW1 lanes */

		if (IS_ELKHARTLAKE(dev_priv) || (INTEL_GEN(dev_priv) >= 12)) {

		if (IS_JSL_EHL(dev_priv) || (INTEL_GEN(dev_priv) >= 12)) {

			tmp = intel_de_read(dev_priv,

					    ICL_PORT_PCS_DW1_AUX(phy));

			tmp &= ~LATENCY_OPTIM_MASK;
@@ -612,7 +612,7 @@ gen11_dsi_setup_dphy_timings(struct intel_encoder *encoder, 
		}

	}



	if (IS_ELKHARTLAKE(dev_priv)) {

	if (IS_JSL_EHL(dev_priv)) {

		for_each_dsi_phy(phy, intel_dsi->phys) {

			tmp = intel_de_read(dev_priv, ICL_DPHY_CHKN(phy));

			tmp |= ICL_DPHY_CHKN_AFE_OVER_PPI_STRAP;

drivers/gpu/drm/i915/display/intel_cdclk.c

+2 −2
Original line number Diff line number Diff line
@@ -2588,7 +2588,7 @@ static int intel_compute_max_dotclk(struct drm_i915_private *dev_priv) 
 */

void intel_update_max_cdclk(struct drm_i915_private *dev_priv)

{

	if (IS_ELKHARTLAKE(dev_priv)) {

	if (IS_JSL_EHL(dev_priv)) {

		if (dev_priv->cdclk.hw.ref == 24000)

			dev_priv->max_cdclk_freq = 552000;

		else
@@ -2829,7 +2829,7 @@ void intel_init_cdclk_hooks(struct drm_i915_private *dev_priv) 
		dev_priv->display.modeset_calc_cdclk = bxt_modeset_calc_cdclk;

		dev_priv->display.calc_voltage_level = tgl_calc_voltage_level;

		dev_priv->cdclk.table = icl_cdclk_table;

	} else if (IS_ELKHARTLAKE(dev_priv)) {

	} else if (IS_JSL_EHL(dev_priv)) {

		dev_priv->display.set_cdclk = bxt_set_cdclk;

		dev_priv->display.bw_calc_min_cdclk = skl_bw_calc_min_cdclk;

		dev_priv->display.modeset_calc_cdclk = bxt_modeset_calc_cdclk;

drivers/gpu/drm/i915/display/intel_combo_phy.c

+3 −3
Original line number Diff line number Diff line
@@ -188,7 +188,7 @@ static bool has_phy_misc(struct drm_i915_private *i915, enum phy phy) 
	 * PHY-B and may not even have instances of the register for the

	 * other combo PHY's.

	 */

	if (IS_ELKHARTLAKE(i915) ||

	if (IS_JSL_EHL(i915) ||

	    IS_ROCKETLAKE(i915) ||

	    IS_DG1(i915))

		return phy < PHY_C;
@@ -283,7 +283,7 @@ static bool icl_combo_phy_verify_state(struct drm_i915_private *dev_priv, 
		ret &= check_phy_reg(dev_priv, phy, ICL_PORT_COMP_DW8(phy),

				     IREFGEN, IREFGEN);



		if (IS_ELKHARTLAKE(dev_priv)) {

		if (IS_JSL_EHL(dev_priv)) {

			if (ehl_vbt_ddi_d_present(dev_priv))

				expected_val = ICL_PHY_MISC_MUX_DDID;
@@ -377,7 +377,7 @@ static void icl_combo_phys_init(struct drm_i915_private *dev_priv) 
		 * "internal" child devices.

		 */

		val = intel_de_read(dev_priv, ICL_PHY_MISC(phy));

		if (IS_ELKHARTLAKE(dev_priv) && phy == PHY_A) {

		if (IS_JSL_EHL(dev_priv) && phy == PHY_A) {

			val &= ~ICL_PHY_MISC_MUX_DDID;



			if (ehl_vbt_ddi_d_present(dev_priv))

drivers/gpu/drm/i915/display/intel_ddi.c

+6 −6
Original line number Diff line number Diff line
@@ -2363,7 +2363,7 @@ static u8 intel_ddi_dp_voltage_max(struct intel_dp *intel_dp, 
		else

			tgl_get_dkl_buf_trans(encoder, crtc_state, &n_entries);

	} else if (INTEL_GEN(dev_priv) == 11) {

		if (IS_ELKHARTLAKE(dev_priv))

		if (IS_JSL_EHL(dev_priv))

			ehl_get_combo_buf_trans(encoder, crtc_state, &n_entries);

		else if (intel_phy_is_combo(dev_priv, phy))

			icl_get_combo_buf_trans(encoder, crtc_state, &n_entries);
@@ -2544,7 +2544,7 @@ static void icl_ddi_combo_vswing_program(struct intel_encoder *encoder, 


	if (INTEL_GEN(dev_priv) >= 12)

		ddi_translations = tgl_get_combo_buf_trans(encoder, crtc_state, &n_entries);

	else if (IS_ELKHARTLAKE(dev_priv))

	else if (IS_JSL_EHL(dev_priv))

		ddi_translations = ehl_get_combo_buf_trans(encoder, crtc_state, &n_entries);

	else

		ddi_translations = icl_get_combo_buf_trans(encoder, crtc_state, &n_entries);
@@ -3135,7 +3135,7 @@ static void intel_ddi_clk_select(struct intel_encoder *encoder, 
		if (!intel_phy_is_combo(dev_priv, phy))

			intel_de_write(dev_priv, DDI_CLK_SEL(port),

				       icl_pll_to_ddi_clk_sel(encoder, crtc_state));

		else if (IS_ELKHARTLAKE(dev_priv) && port >= PORT_C)

		else if (IS_JSL_EHL(dev_priv) && port >= PORT_C)

			/*

			 * MG does not exist but the programming is required

			 * to ungate DDIC and DDID
@@ -3184,7 +3184,7 @@ static void intel_ddi_clk_disable(struct intel_encoder *encoder) 


	if (INTEL_GEN(dev_priv) >= 11) {

		if (!intel_phy_is_combo(dev_priv, phy) ||

		    (IS_ELKHARTLAKE(dev_priv) && port >= PORT_C))

		    (IS_JSL_EHL(dev_priv) && port >= PORT_C))

			intel_de_write(dev_priv, DDI_CLK_SEL(port),

				       DDI_CLK_SEL_NONE);

	} else if (IS_CANNONLAKE(dev_priv)) {
@@ -4328,7 +4328,7 @@ void intel_ddi_compute_min_voltage_level(struct drm_i915_private *dev_priv, 
{

	if (INTEL_GEN(dev_priv) >= 12 && crtc_state->port_clock > 594000)

		crtc_state->min_voltage_level = 2;

	else if (IS_ELKHARTLAKE(dev_priv) && crtc_state->port_clock > 594000)

	else if (IS_JSL_EHL(dev_priv) && crtc_state->port_clock > 594000)

		crtc_state->min_voltage_level = 3;

	else if (INTEL_GEN(dev_priv) >= 11 && crtc_state->port_clock > 594000)

		crtc_state->min_voltage_level = 1;
@@ -5199,7 +5199,7 @@ void intel_ddi_init(struct drm_i915_private *dev_priv, enum port port) 
		encoder->hpd_pin = rkl_hpd_pin(dev_priv, port);

	else if (INTEL_GEN(dev_priv) >= 12)

		encoder->hpd_pin = tgl_hpd_pin(dev_priv, port);

	else if (IS_ELKHARTLAKE(dev_priv))

	else if (IS_JSL_EHL(dev_priv))

		encoder->hpd_pin = ehl_hpd_pin(dev_priv, port);

	else if (IS_GEN(dev_priv, 11))

		encoder->hpd_pin = icl_hpd_pin(dev_priv, port);

drivers/gpu/drm/i915/display/intel_display.c

+4 −4
Original line number Diff line number Diff line
@@ -7331,7 +7331,7 @@ bool intel_phy_is_combo(struct drm_i915_private *dev_priv, enum phy phy) 
		return false;

	else if (IS_ROCKETLAKE(dev_priv))

		return phy <= PHY_D;

	else if (IS_ELKHARTLAKE(dev_priv))

	else if (IS_JSL_EHL(dev_priv))

		return phy <= PHY_C;

	else if (INTEL_GEN(dev_priv) >= 11)

		return phy <= PHY_B;
@@ -7345,7 +7345,7 @@ bool intel_phy_is_tc(struct drm_i915_private *dev_priv, enum phy phy) 
		return false;

	else if (INTEL_GEN(dev_priv) >= 12)

		return phy >= PHY_D && phy <= PHY_I;

	else if (INTEL_GEN(dev_priv) >= 11 && !IS_ELKHARTLAKE(dev_priv))

	else if (INTEL_GEN(dev_priv) >= 11 && !IS_JSL_EHL(dev_priv))

		return phy >= PHY_C && phy <= PHY_F;

	else

		return false;
@@ -7355,7 +7355,7 @@ enum phy intel_port_to_phy(struct drm_i915_private *i915, enum port port) 
{

	if (IS_ROCKETLAKE(i915) && port >= PORT_D)

		return (enum phy)port - 1;

	else if (IS_ELKHARTLAKE(i915) && port == PORT_D)

	else if (IS_JSL_EHL(i915) && port == PORT_D)

		return PHY_A;









	return (enum phy)port;








@@ -17125,7 +17125,7 @@ static void intel_setup_outputs(struct drm_i915_private *dev_priv)







		intel_ddi_init(dev_priv, PORT_H);









		intel_ddi_init(dev_priv, PORT_I);









		icl_dsi_init(dev_priv);









	} else if (IS_ELKHARTLAKE(dev_priv)) {









	} else if (IS_JSL_EHL(dev_priv)) {









		intel_ddi_init(dev_priv, PORT_A);









		intel_ddi_init(dev_priv, PORT_B);









		intel_ddi_init(dev_priv, PORT_C);








































































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