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Fix a problem in early versions of the FPGA IP. In certain situations the IP reports that the FIFO is empty, but a byte is still clocked out. If a flush is done at that point the currently clocked byte is canceled. This causes incompatibilities with the upper layers when a port is closed, it waits until the FIFO is empty and then closes the port. During close the FIFO is flushed -> the last byte is not sent properly. Now the FIFO is only flushed if it is reported to be non-empty. Which makes the currently clocked out byte to finish. [akpm@linux-foundation.org: fix build] Signed-off-by:Richard Röjfors <richard.rojfors@pelagicore.com> Signed-off-by:
Andrew Morton <akpm@linux-foundation.org> Signed-off-by:
Greg Kroah-Hartman <gregkh@suse.de>
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