powerpc/perf: Fix branch event code for power9 (24bedcb7) · Commits · 戴 / test

arch/powerpc/perf/power9-events-list.h

+3 −1

Original line number	Diff line number	Diff line
		@@ -16,7 +16,7 @@ EVENT(PM_CYC, 0x0001e)
		EVENT(PM_ICT_NOSLOT_CYC, 0x100f8)
		EVENT(PM_CMPLU_STALL, 0x1e054)
		EVENT(PM_INST_CMPL, 0x00002)
		EVENT(PM_BRU_CMPL, 0x10012)
		EVENT(PM_BRU_CMPL, 0x4d05e)
		EVENT(PM_BR_MPRED_CMPL, 0x400f6)

		/* All L1 D cache load references counted at finish, gated by reject */
		@@ -56,3 +56,5 @@ EVENT(PM_RUN_CYC, 0x600f4)
		/* Instruction Dispatched */
		EVENT(PM_INST_DISP, 0x200f2)
		EVENT(PM_INST_DISP_ALT, 0x300f2)
		/* Alternate Branch event code */
		EVENT(PM_BR_CMPL_ALT, 0x10012)

+7 −1

Original line number	Diff line number	Diff line
		@@ -231,7 +231,7 @@ static int power9_generic_events_dd1[] = {
		[PERF_COUNT_HW_STALLED_CYCLES_FRONTEND] = PM_ICT_NOSLOT_CYC,
		[PERF_COUNT_HW_STALLED_CYCLES_BACKEND] = PM_CMPLU_STALL,
		[PERF_COUNT_HW_INSTRUCTIONS] = PM_INST_DISP,
		[PERF_COUNT_HW_BRANCH_INSTRUCTIONS] = PM_BRU_CMPL,
		[PERF_COUNT_HW_BRANCH_INSTRUCTIONS] = PM_BR_CMPL_ALT,
		[PERF_COUNT_HW_BRANCH_MISSES] = PM_BR_MPRED_CMPL,
		[PERF_COUNT_HW_CACHE_REFERENCES] = PM_LD_REF_L1,
		[PERF_COUNT_HW_CACHE_MISSES] = PM_LD_MISS_L1_FIN,
		@@ -453,6 +453,12 @@ static int __init init_power9_pmu(void)
		* sampling scenarios in power9 DD1, instead use PM_INST_DISP.
		*/
		EVENT_VAR(PM_INST_CMPL, _g).id = PM_INST_DISP;
		/*
		* Power9 DD1 should use PM_BR_CMPL_ALT event code for
		* "branches" to provide correct counter value.
		*/
		EVENT_VAR(PM_BRU_CMPL, _g).id = PM_BR_CMPL_ALT;
		EVENT_VAR(PM_BRU_CMPL, _c).id = PM_BR_CMPL_ALT;
		rc = register_power_pmu(&power9_isa207_pmu);
		} else {
		rc = register_power_pmu(&power9_pmu);