Commit 24aaed0c authored by Jose Abreu's avatar Jose Abreu Committed by David S. Miller
Browse files

net: stmmac: Uniformize the use of dma_init_* callbacks 



Instead of relying on the GMAC version for choosing if we need to use
dma_init or dma_init_{rx/tx}_chan callback, lets uniformize this and
always use the dma_init_{rx/tx}_chan callbacks.

While at it, fix the use of dma_init_chan callback, which shall be
called for as many channels as the max of rx/tx channels.

Signed-off-by: default avatarJose Abreu <joabreu@synopsys.com>
Cc: David S. Miller <davem@davemloft.net>
Cc: Joao Pinto <jpinto@synopsys.com>
Cc: Vitor Soares <soares@synopsys.com>
Cc: Giuseppe Cavallaro <peppe.cavallaro@st.com>
Cc: Alexandre Torgue <alexandre.torgue@st.com>
Signed-off-by: default avatarDavid S. Miller <davem@davemloft.net>
parent 758d5c73

drivers/net/ethernet/stmicro/stmmac/dwmac-sun8i.c

+19 −6
Original line number Diff line number Diff line
@@ -276,17 +276,28 @@ static int sun8i_dwmac_dma_reset(void __iomem *ioaddr) 
 * Called from stmmac via stmmac_dma_ops->init

 */

static void sun8i_dwmac_dma_init(void __iomem *ioaddr,

				 struct stmmac_dma_cfg *dma_cfg,

				 u32 dma_tx, u32 dma_rx, int atds)

				 struct stmmac_dma_cfg *dma_cfg, int atds)

{

	/* Write TX and RX descriptors address */

	writel(dma_rx, ioaddr + EMAC_RX_DESC_LIST);

	writel(dma_tx, ioaddr + EMAC_TX_DESC_LIST);



	writel(EMAC_RX_INT | EMAC_TX_INT, ioaddr + EMAC_INT_EN);

	writel(0x1FFFFFF, ioaddr + EMAC_INT_STA);

}



static void sun8i_dwmac_dma_init_rx(void __iomem *ioaddr,

				    struct stmmac_dma_cfg *dma_cfg,

				    u32 dma_rx_phy, u32 chan)

{

	/* Write RX descriptors address */

	writel(dma_rx_phy, ioaddr + EMAC_RX_DESC_LIST);

}



static void sun8i_dwmac_dma_init_tx(void __iomem *ioaddr,

				    struct stmmac_dma_cfg *dma_cfg,

				    u32 dma_tx_phy, u32 chan)

{

	/* Write TX descriptors address */

	writel(dma_tx_phy, ioaddr + EMAC_TX_DESC_LIST);

}



/* sun8i_dwmac_dump_regs() - Dump EMAC address space

 * Called from stmmac_dma_ops->dump_regs

 * Used for ethtool
@@ -492,6 +503,8 @@ static void sun8i_dwmac_dma_operation_mode_tx(void __iomem *ioaddr, int mode, 
static const struct stmmac_dma_ops sun8i_dwmac_dma_ops = {

	.reset = sun8i_dwmac_dma_reset,

	.init = sun8i_dwmac_dma_init,

	.init_rx_chan = sun8i_dwmac_dma_init_rx,

	.init_tx_chan = sun8i_dwmac_dma_init_tx,

	.dump_regs = sun8i_dwmac_dump_regs,

	.dma_rx_mode = sun8i_dwmac_dma_operation_mode_rx,

	.dma_tx_mode = sun8i_dwmac_dma_operation_mode_tx,

drivers/net/ethernet/stmicro/stmmac/dwmac1000_dma.c

+18 −7
Original line number Diff line number Diff line
@@ -81,8 +81,7 @@ static void dwmac1000_dma_axi(void __iomem *ioaddr, struct stmmac_axi *axi) 
}



static void dwmac1000_dma_init(void __iomem *ioaddr,

			       struct stmmac_dma_cfg *dma_cfg,

			       u32 dma_tx, u32 dma_rx, int atds)

			       struct stmmac_dma_cfg *dma_cfg, int atds)

{

	u32 value = readl(ioaddr + DMA_BUS_MODE);

	int txpbl = dma_cfg->txpbl ?: dma_cfg->pbl;
@@ -119,12 +118,22 @@ static void dwmac1000_dma_init(void __iomem *ioaddr, 


	/* Mask interrupts by writing to CSR7 */

	writel(DMA_INTR_DEFAULT_MASK, ioaddr + DMA_INTR_ENA);

}



	/* RX/TX descriptor base address lists must be written into

	 * DMA CSR3 and CSR4, respectively

	 */

	writel(dma_tx, ioaddr + DMA_TX_BASE_ADDR);

	writel(dma_rx, ioaddr + DMA_RCV_BASE_ADDR);

static void dwmac1000_dma_init_rx(void __iomem *ioaddr,

				  struct stmmac_dma_cfg *dma_cfg,

				  u32 dma_rx_phy, u32 chan)

{

	/* RX descriptor base address list must be written into DMA CSR3 */

	writel(dma_rx_phy, ioaddr + DMA_RCV_BASE_ADDR);

}



static void dwmac1000_dma_init_tx(void __iomem *ioaddr,

				  struct stmmac_dma_cfg *dma_cfg,

				  u32 dma_tx_phy, u32 chan)

{

	/* TX descriptor base address list must be written into DMA CSR4 */

	writel(dma_tx_phy, ioaddr + DMA_TX_BASE_ADDR);

}



static u32 dwmac1000_configure_fc(u32 csr6, int rxfifosz)
@@ -264,6 +273,8 @@ static void dwmac1000_rx_watchdog(void __iomem *ioaddr, u32 riwt, 
const struct stmmac_dma_ops dwmac1000_dma_ops = {

	.reset = dwmac_dma_reset,

	.init = dwmac1000_dma_init,

	.init_rx_chan = dwmac1000_dma_init_rx,

	.init_tx_chan = dwmac1000_dma_init_tx,

	.axi = dwmac1000_dma_axi,

	.dump_regs = dwmac1000_dump_dma_regs,

	.dma_rx_mode = dwmac1000_dma_operation_mode_rx,

drivers/net/ethernet/stmicro/stmmac/dwmac100_dma.c

+18 −7
Original line number Diff line number Diff line
@@ -29,8 +29,7 @@ 
#include "dwmac_dma.h"



static void dwmac100_dma_init(void __iomem *ioaddr,

			      struct stmmac_dma_cfg *dma_cfg,

			      u32 dma_tx, u32 dma_rx, int atds)

			      struct stmmac_dma_cfg *dma_cfg, int atds)

{

	/* Enable Application Access by writing to DMA CSR0 */

	writel(DMA_BUS_MODE_DEFAULT | (dma_cfg->pbl << DMA_BUS_MODE_PBL_SHIFT),
@@ -38,12 +37,22 @@ static void dwmac100_dma_init(void __iomem *ioaddr, 


	/* Mask interrupts by writing to CSR7 */

	writel(DMA_INTR_DEFAULT_MASK, ioaddr + DMA_INTR_ENA);

}



	/* RX/TX descriptor base addr lists must be written into

	 * DMA CSR3 and CSR4, respectively

	 */

	writel(dma_tx, ioaddr + DMA_TX_BASE_ADDR);

	writel(dma_rx, ioaddr + DMA_RCV_BASE_ADDR);

static void dwmac100_dma_init_rx(void __iomem *ioaddr,

				 struct stmmac_dma_cfg *dma_cfg,

				 u32 dma_rx_phy, u32 chan)

{

	/* RX descriptor base addr lists must be written into DMA CSR3 */

	writel(dma_rx_phy, ioaddr + DMA_RCV_BASE_ADDR);

}



static void dwmac100_dma_init_tx(void __iomem *ioaddr,

				 struct stmmac_dma_cfg *dma_cfg,

				 u32 dma_tx_phy, u32 chan)

{

	/* TX descriptor base addr lists must be written into DMA CSR4 */

	writel(dma_tx_phy, ioaddr + DMA_TX_BASE_ADDR);

}



/* Store and Forward capability is not used at all.
@@ -112,6 +121,8 @@ static void dwmac100_dma_diagnostic_fr(void *data, struct stmmac_extra_stats *x, 
const struct stmmac_dma_ops dwmac100_dma_ops = {

	.reset = dwmac_dma_reset,

	.init = dwmac100_dma_init,

	.init_rx_chan = dwmac100_dma_init_rx,

	.init_tx_chan = dwmac100_dma_init_tx,

	.dump_regs = dwmac100_dump_dma_regs,

	.dma_tx_mode = dwmac100_dma_operation_mode_tx,

	.dma_diagnostic_fr = dwmac100_dma_diagnostic_fr,

drivers/net/ethernet/stmicro/stmmac/dwmac4_dma.c

+1 −2
Original line number Diff line number Diff line
@@ -120,8 +120,7 @@ static void dwmac4_dma_init_channel(void __iomem *ioaddr, 
}



static void dwmac4_dma_init(void __iomem *ioaddr,

			    struct stmmac_dma_cfg *dma_cfg,

			    u32 dma_tx, u32 dma_rx, int atds)

			    struct stmmac_dma_cfg *dma_cfg, int atds)

{

	u32 value = readl(ioaddr + DMA_SYS_BUS_MODE);

drivers/net/ethernet/stmicro/stmmac/hwif.h

+1 −1
Original line number Diff line number Diff line
@@ -140,7 +140,7 @@ struct stmmac_dma_ops { 
	/* DMA core initialization */

	int (*reset)(void __iomem *ioaddr);

	void (*init)(void __iomem *ioaddr, struct stmmac_dma_cfg *dma_cfg,

		     u32 dma_tx, u32 dma_rx, int atds);

		     int atds);

	void (*init_chan)(void __iomem *ioaddr,

			  struct stmmac_dma_cfg *dma_cfg, u32 chan);

	void (*init_rx_chan)(void __iomem *ioaddr,

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