Commit 245bbe80 authored by Miquel Raynal's avatar Miquel Raynal
Browse files

Merge tag 'spi-nor/for-5.7' into mtd/next 

SPI NOR core changes:
- move all the manufacturer specific quirks/code out of the core,
to make the core logic more readable and thus ease maintenance.
- move the SFDP logic out of the core, it provides a better
separation between the SFDP parsing and core logic.
- trim what is exposed in spi-nor.h. The SPI NOR controllers drivers
must not be able to use structures that are meant just for the
SPI NOR core.
- use the spi-mem direct mapping API to let advanced controllers
optimize the read/write operations when they support direct mapping.
- add generic formula for the Status Register block protection
handling. It fixes some long standing locking limitations and eases
the addition of the 4bit block protection support.
- add block protection support for flashes with 4 block protection
bits in the Status Register.

SPI NOR controller drivers changes:
- the mtk-quadspi driver is replaced by the new spi-mem
spi-mtk-nor driver. Merge tag 'mtk-mtd-spi-move' into spi-nor/next
to avoid conflicts.
parents 176538d9 f3f2b7eb

Documentation/devicetree/bindings/mtd/mtk-quadspi.txt→Documentation/devicetree/bindings/spi/spi-mtk-nor.txt

+6 −9
Original line number Diff line number Diff line 
* Serial NOR flash controller for MediaTek SoCs

* Serial NOR flash controller for MediaTek ARM SoCs



Required properties:

- compatible: 	  For mt8173, compatible should be "mediatek,mt8173-nor",
@@ -13,6 +13,7 @@ Required properties: 
		  "mediatek,mt7629-nor", "mediatek,mt8173-nor"

		  "mediatek,mt8173-nor"

- reg: 		  physical base address and length of the controller's register

- interrupts:	  Interrupt number used by the controller.

- clocks: 	  the phandle of the clocks needed by the nor controller

- clock-names: 	  the names of the clocks

		  the clocks should be named "spi" and "sf". "spi" is used for spi bus,
@@ -22,20 +23,16 @@ Required properties: 
- #address-cells: should be <1>

- #size-cells:	  should be <0>



The SPI flash must be a child of the nor_flash node and must have a

compatible property. Also see jedec,spi-nor.txt.



Required properties:

- compatible:	  May include a device-specific string consisting of the manufacturer

		  and name of the chip. Must also include "jedec,spi-nor" for any

		  SPI NOR flash that can be identified by the JEDEC READ ID opcode (0x9F).

- reg :		  Chip-Select number

There should be only one spi slave device following generic spi bindings.

It's not recommended to use this controller for devices other than SPI NOR

flash due to limited transfer capability of this controller.



Example:



nor_flash: spi@1100d000 {

	compatible = "mediatek,mt8173-nor";

	reg = <0 0x1100d000 0 0xe0>;

	interrupts = <&spi_flash_irq>;

	clocks = <&pericfg CLK_PERI_SPI>,

		 <&topckgen CLK_TOP_SPINFI_IFR_SEL>;

	clock-names = "spi", "sf";

MAINTAINERS

+1 −1
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@@ -1928,7 +1928,7 @@ F: Documentation/devicetree/bindings/i2c/i2c-lpc2k.txt 
F:	arch/arm/boot/dts/lpc43*

F:	drivers/i2c/busses/i2c-lpc2k.c

F:	drivers/memory/pl172.c

F:	drivers/mtd/spi-nor/nxp-spifi.c

F:	drivers/mtd/spi-nor/controllers/nxp-spifi.c

F:	drivers/rtc/rtc-lpc24xx.c

N:	lpc18xx

































drivers/mtd/spi-nor/Kconfig



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@@ -24,87 +24,6 @@ config MTD_SPI_NOR_USE_4K_SECTORS













	  Please note that some tools/drivers/filesystems may not work with















	  4096 B erase size (e.g. UBIFS requires 15 KiB as a minimum).





























config SPI_ASPEED_SMC













	tristate "Aspeed flash controllers in SPI mode"













	depends on ARCH_ASPEED || COMPILE_TEST













	depends on HAS_IOMEM && OF













	help













	  This enables support for the Firmware Memory controller (FMC)













	  in the Aspeed AST2500/AST2400 SoCs when attached to SPI NOR chips,













	  and support for the SPI flash memory controller (SPI) for













	  the host firmware. The implementation only supports SPI NOR.



























config SPI_CADENCE_QUADSPI













	tristate "Cadence Quad SPI controller"













	depends on OF && (ARM || ARM64 || COMPILE_TEST)













	help













	  Enable support for the Cadence Quad SPI Flash controller.



























	  Cadence QSPI is a specialized controller for connecting an SPI













	  Flash over 1/2/4-bit wide bus. Enable this option if you have a













	  device with a Cadence QSPI controller and want to access the













	  Flash as an MTD device.



























config SPI_HISI_SFC













	tristate "Hisilicon FMC SPI-NOR Flash Controller(SFC)"













	depends on ARCH_HISI || COMPILE_TEST













	depends on HAS_IOMEM













	help













	  This enables support for HiSilicon FMC SPI-NOR flash controller.



























config SPI_MTK_QUADSPI













	tristate "MediaTek Quad SPI controller"













	depends on HAS_IOMEM













	help













	  This enables support for the Quad SPI controller in master mode.













	  This controller does not support generic SPI. It only supports













	  SPI NOR.



























config SPI_NXP_SPIFI













	tristate "NXP SPI Flash Interface (SPIFI)"













	depends on OF && (ARCH_LPC18XX || COMPILE_TEST)













	depends on HAS_IOMEM













	help













	  Enable support for the NXP LPC SPI Flash Interface controller.



























	  SPIFI is a specialized controller for connecting serial SPI













	  Flash. Enable this option if you have a device with a SPIFI













	  controller and want to access the Flash as a mtd device.



























config SPI_INTEL_SPI













	tristate



























config SPI_INTEL_SPI_PCI













	tristate "Intel PCH/PCU SPI flash PCI driver (DANGEROUS)"













	depends on X86 && PCI













	select SPI_INTEL_SPI













	help













	  This enables PCI support for the Intel PCH/PCU SPI controller in













	  master mode. This controller is present in modern Intel hardware













	  and is used to hold BIOS and other persistent settings. Using













	  this driver it is possible to upgrade BIOS directly from Linux.



























	  Say N here unless you know what you are doing. Overwriting the













	  SPI flash may render the system unbootable.



























	  To compile this driver as a module, choose M here: the module













	  will be called intel-spi-pci.



























config SPI_INTEL_SPI_PLATFORM













	tristate "Intel PCH/PCU SPI flash platform driver (DANGEROUS)"













	depends on X86













	select SPI_INTEL_SPI













	help













	  This enables platform support for the Intel PCH/PCU SPI













	  controller in master mode. This controller is present in modern













	  Intel hardware and is used to hold BIOS and other persistent













	  settings. Using this driver it is possible to upgrade BIOS













	  directly from Linux.



























	  Say N here unless you know what you are doing. Overwriting the













	  SPI flash may render the system unbootable.



























	  To compile this driver as a module, choose M here: the module













	  will be called intel-spi-platform.













source "drivers/mtd/spi-nor/controllers/Kconfig"































endif # MTD_SPI_NOR
























drivers/mtd/spi-nor/Makefile



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# SPDX-License-Identifier: GPL-2.0



























spi-nor-objs			:= core.o sfdp.o













spi-nor-objs			+= atmel.o













spi-nor-objs			+= catalyst.o













spi-nor-objs			+= eon.o













spi-nor-objs			+= esmt.o













spi-nor-objs			+= everspin.o













spi-nor-objs			+= fujitsu.o













spi-nor-objs			+= gigadevice.o













spi-nor-objs			+= intel.o













spi-nor-objs			+= issi.o













spi-nor-objs			+= macronix.o













spi-nor-objs			+= micron-st.o













spi-nor-objs			+= spansion.o













spi-nor-objs			+= sst.o













spi-nor-objs			+= winbond.o













spi-nor-objs			+= xilinx.o













spi-nor-objs			+= xmc.o















obj-$(CONFIG_MTD_SPI_NOR)	+= spi-nor.o












obj-$(CONFIG_SPI_ASPEED_SMC)	+= aspeed-smc.o













obj-$(CONFIG_SPI_CADENCE_QUADSPI)	+= cadence-quadspi.o













obj-$(CONFIG_SPI_HISI_SFC)	+= hisi-sfc.o













obj-$(CONFIG_SPI_MTK_QUADSPI)    += mtk-quadspi.o













obj-$(CONFIG_SPI_NXP_SPIFI)	+= nxp-spifi.o













obj-$(CONFIG_SPI_INTEL_SPI)	+= intel-spi.o













obj-$(CONFIG_SPI_INTEL_SPI_PCI)	+= intel-spi-pci.o













obj-$(CONFIG_SPI_INTEL_SPI_PLATFORM)	+= intel-spi-platform.o
























drivers/mtd/spi-nor/atmel.c
0 → 100644



+46
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// SPDX-License-Identifier: GPL-2.0













/*













 * Copyright (C) 2005, Intec Automation Inc.













 * Copyright (C) 2014, Freescale Semiconductor, Inc.













 */



























#include <linux/mtd/spi-nor.h>



























#include "core.h"



























static const struct flash_info atmel_parts[] = {













	/* Atmel -- some are (confusingly) marketed as "DataFlash" */













	{ "at25fs010",  INFO(0x1f6601, 0, 32 * 1024,   4, SECT_4K) },













	{ "at25fs040",  INFO(0x1f6604, 0, 64 * 1024,   8, SECT_4K) },



























	{ "at25df041a", INFO(0x1f4401, 0, 64 * 1024,   8, SECT_4K) },













	{ "at25df321",  INFO(0x1f4700, 0, 64 * 1024,  64, SECT_4K) },













	{ "at25df321a", INFO(0x1f4701, 0, 64 * 1024,  64, SECT_4K) },













	{ "at25df641",  INFO(0x1f4800, 0, 64 * 1024, 128, SECT_4K) },



























	{ "at25sl321",	INFO(0x1f4216, 0, 64 * 1024, 64,













			     SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) },



























	{ "at26f004",   INFO(0x1f0400, 0, 64 * 1024,  8, SECT_4K) },













	{ "at26df081a", INFO(0x1f4501, 0, 64 * 1024, 16, SECT_4K) },













	{ "at26df161a", INFO(0x1f4601, 0, 64 * 1024, 32, SECT_4K) },













	{ "at26df321",  INFO(0x1f4700, 0, 64 * 1024, 64, SECT_4K) },



























	{ "at45db081d", INFO(0x1f2500, 0, 64 * 1024, 16, SECT_4K) },













};



























static void atmel_default_init(struct spi_nor *nor)













{













	nor->flags |= SNOR_F_HAS_LOCK;













}



























static const struct spi_nor_fixups atmel_fixups = {













	.default_init = atmel_default_init,













};



























const struct spi_nor_manufacturer spi_nor_atmel = {













	.name = "atmel",













	.parts = atmel_parts,













	.nparts = ARRAY_SIZE(atmel_parts),













	.fixups = &atmel_fixups,













};
































































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