Commit 240abb3c authored by Lucas De Marchi's avatar Lucas De Marchi
Browse files

drm/i915/dg1: Add DG1 power wells 



TGL power wells can be re-used for DG1 with the exception of the fake
power well for TC_COLD.

v2: use logic to skip power wells while copying instead of duplicating
the definition of TGL power wells (Matt Roper)

Bspec: 49182

Cc: Matt Roper <matthew.d.roper@intel.com>
Cc: Anshuman Gupta <anshuman.gupta@intel.com>
Signed-off-by: default avatarLucas De Marchi <lucas.demarchi@intel.com>
Reviewed-by: default avatarMatt Roper <matthew.d.roper@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20201014191937.1266226-3-lucas.demarchi@intel.com
parent 62277f33

drivers/gpu/drm/i915/display/intel_display_power.c

+5 −2
Original line number Diff line number Diff line
@@ -4150,7 +4150,7 @@ static const struct i915_power_well_desc tgl_power_wells[] = { 
		.name = "TC cold off",

		.domains = TGL_TC_COLD_OFF_POWER_DOMAINS,

		.ops = &tgl_tc_cold_off_ops,

		.id = DISP_PW_ID_NONE,

		.id = TGL_DISP_PW_TC_COLD_OFF,

	},

	{

		.name = "AUX A",
@@ -4634,7 +4634,10 @@ int intel_power_domains_init(struct drm_i915_private *dev_priv) 
	 * The enabling order will be from lower to higher indexed wells,

	 * the disabling order is reversed.

	 */

	if (IS_ROCKETLAKE(dev_priv)) {

	if (IS_DG1(dev_priv)) {

		err = set_power_wells_mask(power_domains, tgl_power_wells,

					   BIT_ULL(TGL_DISP_PW_TC_COLD_OFF));

	} else if (IS_ROCKETLAKE(dev_priv)) {

		err = set_power_wells(power_domains, rkl_power_wells);

	} else if (IS_GEN(dev_priv, 12)) {

		err = set_power_wells(power_domains, tgl_power_wells);

drivers/gpu/drm/i915/display/intel_display_power.h

+1 −0
Original line number Diff line number Diff line
@@ -105,6 +105,7 @@ enum i915_power_well_id { 
	CNL_DISP_PW_DDI_F_AUX,

	ICL_DISP_PW_3,

	SKL_DISP_DC_OFF,

	TGL_DISP_PW_TC_COLD_OFF,

};



#define POWER_DOMAIN_PIPE(pipe) ((pipe) + POWER_DOMAIN_PIPE_A)

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