Commit 23ec3d14 authored by Rex Zhu's avatar Rex Zhu Committed by Alex Deucher
Browse files

drm/amd/pp: Convert clock unit to KHz as defined 



Convert clock unit 10KHz to KHz as the data sturct defined.
e.g.
struct pp_clock_with_latency {
	uint32_t clocks_in_khz;
	uint32_t latency_in_us;
};
Meanwhile revert the same conversion in display side.

Acked-by: default avatarAlex Deucher <alexander.deucher@amd.com>
Acked-by: default avatarHarry Wentland <harry.wentland@amd.com>
Signed-off-by: default avatarRex Zhu <Rex.Zhu@amd.com>
Signed-off-by: default avatarAlex Deucher <alexander.deucher@amd.com>
parent afb1436c

drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_pp_smu.c

+7 −11
Original line number Diff line number Diff line
@@ -203,8 +203,7 @@ static void pp_to_dc_clock_levels( 


	for (i = 0; i < dc_clks->num_levels; i++) {

		DRM_INFO("DM_PPLIB:\t %d\n", pp_clks->clock[i]);

		/* translate 10kHz to kHz */

		dc_clks->clocks_in_khz[i] = pp_clks->clock[i] * 10;

		dc_clks->clocks_in_khz[i] = pp_clks->clock[i];

	}

}
@@ -229,9 +228,8 @@ static void pp_to_dc_clock_levels_with_latency( 
			DC_DECODE_PP_CLOCK_TYPE(dc_clk_type));



	for (i = 0; i < clk_level_info->num_levels; i++) {

		DRM_DEBUG("DM_PPLIB:\t %d in 10kHz\n", pp_clks->data[i].clocks_in_khz);

		/* translate 10kHz to kHz */

		clk_level_info->data[i].clocks_in_khz = pp_clks->data[i].clocks_in_khz * 10;

		DRM_DEBUG("DM_PPLIB:\t %d in kHz\n", pp_clks->data[i].clocks_in_khz);

		clk_level_info->data[i].clocks_in_khz = pp_clks->data[i].clocks_in_khz;

		clk_level_info->data[i].latency_in_us = pp_clks->data[i].latency_in_us;

	}

}
@@ -257,9 +255,8 @@ static void pp_to_dc_clock_levels_with_voltage( 
			DC_DECODE_PP_CLOCK_TYPE(dc_clk_type));



	for (i = 0; i < clk_level_info->num_levels; i++) {

		DRM_INFO("DM_PPLIB:\t %d in 10kHz\n", pp_clks->data[i].clocks_in_khz);

		/* translate 10kHz to kHz */

		clk_level_info->data[i].clocks_in_khz = pp_clks->data[i].clocks_in_khz * 10;

		DRM_INFO("DM_PPLIB:\t %d in kHz\n", pp_clks->data[i].clocks_in_khz);

		clk_level_info->data[i].clocks_in_khz = pp_clks->data[i].clocks_in_khz;

		clk_level_info->data[i].voltage_in_mv = pp_clks->data[i].voltage_in_mv;

	}

}
@@ -434,9 +431,8 @@ bool dm_pp_get_static_clocks( 
		return false;



	static_clk_info->max_clocks_state = pp_clk_info.max_clocks_state;

	/* translate 10kHz to kHz */

	static_clk_info->max_mclk_khz = pp_clk_info.max_memory_clock * 10;

	static_clk_info->max_sclk_khz = pp_clk_info.max_engine_clock * 10;

	static_clk_info->max_mclk_khz = pp_clk_info.max_memory_clock;

	static_clk_info->max_sclk_khz = pp_clk_info.max_engine_clock;



	return true;

}

drivers/gpu/drm/amd/powerplay/hwmgr/smu10_hwmgr.c

+2 −2
Original line number Diff line number Diff line
@@ -993,7 +993,7 @@ static int smu10_get_clock_by_type_with_latency(struct pp_hwmgr *hwmgr, 


	clocks->num_levels = 0;

	for (i = 0; i < pclk_vol_table->count; i++) {

		clocks->data[i].clocks_in_khz = pclk_vol_table->entries[i].clk;

		clocks->data[i].clocks_in_khz = pclk_vol_table->entries[i].clk * 10;

		clocks->data[i].latency_in_us = latency_required ?

						smu10_get_mem_latency(hwmgr,

						pclk_vol_table->entries[i].clk) :
@@ -1044,7 +1044,7 @@ static int smu10_get_clock_by_type_with_voltage(struct pp_hwmgr *hwmgr, 


	clocks->num_levels = 0;

	for (i = 0; i < pclk_vol_table->count; i++) {

		clocks->data[i].clocks_in_khz = pclk_vol_table->entries[i].clk;

		clocks->data[i].clocks_in_khz = pclk_vol_table->entries[i].clk  * 10;

		clocks->data[i].voltage_in_mv = pclk_vol_table->entries[i].vol;

		clocks->num_levels++;

	}

drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c

+16 −18
Original line number Diff line number Diff line
@@ -4064,10 +4064,11 @@ static void vega10_get_sclks(struct pp_hwmgr *hwmgr, 
			table_info->vdd_dep_on_sclk;

	uint32_t i;



	clocks->num_levels = 0;

	for (i = 0; i < dep_table->count; i++) {

		if (dep_table->entries[i].clk) {

			clocks->data[clocks->num_levels].clocks_in_khz =

					dep_table->entries[i].clk;

					dep_table->entries[i].clk * 10;

			clocks->num_levels++;

		}

	}
@@ -4094,26 +4095,23 @@ static void vega10_get_memclocks(struct pp_hwmgr *hwmgr, 
	struct phm_ppt_v1_clock_voltage_dependency_table *dep_table =

			table_info->vdd_dep_on_mclk;

	struct vega10_hwmgr *data = hwmgr->backend;

	uint32_t j = 0;

	uint32_t i;



	clocks->num_levels = 0;

	data->mclk_latency_table.count = 0;



	for (i = 0; i < dep_table->count; i++) {

		if (dep_table->entries[i].clk) {

			clocks->data[clocks->num_levels].clocks_in_khz =

			data->mclk_latency_table.entries

			[data->mclk_latency_table.count].frequency =

			clocks->data[j].clocks_in_khz =

						dep_table->entries[i].clk * 10;

			data->mclk_latency_table.entries[j].frequency =

							dep_table->entries[i].clk;

			clocks->data[clocks->num_levels].latency_in_us =

			data->mclk_latency_table.entries

			[data->mclk_latency_table.count].latency =

			clocks->data[j].latency_in_us =

				data->mclk_latency_table.entries[j].latency =

						vega10_get_mem_latency(hwmgr,

							dep_table->entries[i].clk);

			clocks->num_levels++;

			data->mclk_latency_table.count++;

			j++;

		}

	}

	clocks->num_levels = data->mclk_latency_table.count = j;

}



static void vega10_get_dcefclocks(struct pp_hwmgr *hwmgr,
@@ -4126,7 +4124,7 @@ static void vega10_get_dcefclocks(struct pp_hwmgr *hwmgr, 
	uint32_t i;



	for (i = 0; i < dep_table->count; i++) {

		clocks->data[i].clocks_in_khz = dep_table->entries[i].clk;

		clocks->data[i].clocks_in_khz = dep_table->entries[i].clk * 10;

		clocks->data[i].latency_in_us = 0;

		clocks->num_levels++;

	}
@@ -4142,7 +4140,7 @@ static void vega10_get_socclocks(struct pp_hwmgr *hwmgr, 
	uint32_t i;



	for (i = 0; i < dep_table->count; i++) {

		clocks->data[i].clocks_in_khz = dep_table->entries[i].clk;

		clocks->data[i].clocks_in_khz = dep_table->entries[i].clk * 10;

		clocks->data[i].latency_in_us = 0;

		clocks->num_levels++;

	}
@@ -4202,7 +4200,7 @@ static int vega10_get_clock_by_type_with_voltage(struct pp_hwmgr *hwmgr, 
	}



	for (i = 0; i < dep_table->count; i++) {

		clocks->data[i].clocks_in_khz = dep_table->entries[i].clk;

		clocks->data[i].clocks_in_khz = dep_table->entries[i].clk  * 10;

		clocks->data[i].voltage_in_mv = (uint32_t)(table_info->vddc_lookup_table->

				entries[dep_table->entries[i].vddInd].us_vdd);

		clocks->num_levels++;

drivers/gpu/drm/amd/powerplay/hwmgr/vega12_hwmgr.c

+9 −11
Original line number Diff line number Diff line
@@ -1645,7 +1645,7 @@ static int vega12_get_sclks(struct pp_hwmgr *hwmgr, 


	for (i = 0; i < ucount; i++) {

		clocks->data[i].clocks_in_khz =

			dpm_table->dpm_levels[i].value * 100;

			dpm_table->dpm_levels[i].value * 1000;



		clocks->data[i].latency_in_us = 0;

	}
@@ -1676,10 +1676,8 @@ static int vega12_get_memclocks(struct pp_hwmgr *hwmgr, 
		MAX_NUM_CLOCKS : dpm_table->count;



	for (i = 0; i < ucount; i++) {

		clocks->data[i].clocks_in_khz =

			data->mclk_latency_table.entries[i].frequency =

			dpm_table->dpm_levels[i].value * 100;



		clocks->data[i].clocks_in_khz = dpm_table->dpm_levels[i].value * 1000;

		data->mclk_latency_table.entries[i].frequency = dpm_table->dpm_levels[i].value * 100;

		clocks->data[i].latency_in_us =

			data->mclk_latency_table.entries[i].latency =

			vega12_get_mem_latency(hwmgr, dpm_table->dpm_levels[i].value);
@@ -1708,7 +1706,7 @@ static int vega12_get_dcefclocks(struct pp_hwmgr *hwmgr, 


	for (i = 0; i < ucount; i++) {

		clocks->data[i].clocks_in_khz =

			dpm_table->dpm_levels[i].value * 100;

			dpm_table->dpm_levels[i].value * 1000;



		clocks->data[i].latency_in_us = 0;

	}
@@ -1736,7 +1734,7 @@ static int vega12_get_socclocks(struct pp_hwmgr *hwmgr, 


	for (i = 0; i < ucount; i++) {

		clocks->data[i].clocks_in_khz =

			dpm_table->dpm_levels[i].value * 100;

			dpm_table->dpm_levels[i].value * 1000;



		clocks->data[i].latency_in_us = 0;

	}
@@ -1918,8 +1916,8 @@ static int vega12_print_clock_levels(struct pp_hwmgr *hwmgr, 
				return -1);

		for (i = 0; i < clocks.num_levels; i++)

			size += sprintf(buf + size, "%d: %uMhz %s\n",

				i, clocks.data[i].clocks_in_khz / 100,

				(clocks.data[i].clocks_in_khz == now) ? "*" : "");

				i, clocks.data[i].clocks_in_khz / 1000,

				(clocks.data[i].clocks_in_khz / 1000 == now) ? "*" : "");

		break;



	case PP_MCLK:
@@ -1934,8 +1932,8 @@ static int vega12_print_clock_levels(struct pp_hwmgr *hwmgr, 
				return -1);

		for (i = 0; i < clocks.num_levels; i++)

			size += sprintf(buf + size, "%d: %uMhz %s\n",

				i, clocks.data[i].clocks_in_khz / 100,

				(clocks.data[i].clocks_in_khz == now) ? "*" : "");

				i, clocks.data[i].clocks_in_khz / 1000,

				(clocks.data[i].clocks_in_khz / 1000 == now) ? "*" : "");

		break;



	case PP_PCIE:

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