Commit 23d1c515 authored by Catalin Marinas's avatar Catalin Marinas
Browse files

ARMv7: Document the PRRR and NMRR registers setting 



This patch adds a comment to the proc-v7.S file for the setting of the
PRRR and NMRR registers. It also sets the PRRR[13:12] bits to 0
(corresponding to the reserved TEX[0]CB encoding 110) to be consistent
with the documentation.

Signed-off-by: default avatarCatalin Marinas <catalin.marinas@arm.com>
parent 213fb2a8

arch/arm/mm/proc-v7.S

+30 −2
Original line number Diff line number Diff line
@@ -219,8 +219,36 @@ __v7_setup: 
	mov	r10, #0x1f			@ domains 0, 1 = manager

	mcr	p15, 0, r10, c3, c0, 0		@ load domain access register

#endif

	ldr	r5, =0xff0aa1a8

	ldr	r6, =0x40e040e0

	/*

	 * Memory region attributes with SCTLR.TRE=1

	 *

	 *   n = TEX[0],C,B

	 *   TR = PRRR[2n+1:2n]		- memory type

	 *   IR = NMRR[2n+1:2n]		- inner cacheable property

	 *   OR = NMRR[2n+17:2n+16]	- outer cacheable property

	 *

	 *			n	TR	IR	OR

	 *   UNCACHED		000	00

	 *   BUFFERABLE		001	10	00	00

	 *   WRITETHROUGH	010	10	10	10

	 *   WRITEBACK		011	10	11	11

	 *   reserved		110

	 *   WRITEALLOC		111	10	01	01

	 *   DEV_SHARED		100	01

	 *   DEV_NONSHARED	100	01

	 *   DEV_WC		001	10

	 *   DEV_CACHED		011	10

	 *

	 * Other attributes:

	 *

	 *   DS0 = PRRR[16] = 0		- device shareable property

	 *   DS1 = PRRR[17] = 1		- device shareable property

	 *   NS0 = PRRR[18] = 0		- normal shareable property

	 *   NS1 = PRRR[19] = 1		- normal shareable property

	 *   NOS = PRRR[24+n] = 1	- not outer shareable

	 */

	ldr	r5, =0xff0a81a8			@ PRRR

	ldr	r6, =0x40e040e0			@ NMRR

	mcr	p15, 0, r5, c10, c2, 0		@ write PRRR

	mcr	p15, 0, r6, c10, c2, 1		@ write NMRR

	adr	r5, v7_crval

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