Commit 23c8f88e authored by Archit Taneja's avatar Archit Taneja Committed by Tomi Valkeinen
Browse files

OMAPDSS: Add interlace parameter to omap_video_timings 



Add a parameter called interlace which tells whether the timings are in
interlaced or progressive mode. This aligns the omap_video_timings struct with
the Xorg modeline configuration.

It also removes the hack needed to write to divide the manager height by 2 if
the connected interface is VENC.

Signed-off-by: default avatarArchit Taneja <archit@ti.com>
parent 07fb51c6

drivers/video/omap2/dss/dispc.c

+1 −5
Original line number Diff line number Diff line
@@ -2754,11 +2754,7 @@ void dispc_mgr_set_timings(enum omap_channel channel, 


		DSSDBG("hsync %luHz, vsync %luHz\n", ht, vt);

	} else {

		enum dss_hdmi_venc_clk_source_select source;



		source = dss_get_hdmi_venc_clk_source();



		if (source == DSS_VENC_TV_CLK)

		if (t.interlace == true)

			t.y_res /= 2;

	}

drivers/video/omap2/dss/hdmi_panel.c

+1 −0
Original line number Diff line number Diff line
@@ -46,6 +46,7 @@ static int hdmi_panel_probe(struct omap_dss_device *dssdev) 
	dssdev->panel.timings = (struct omap_video_timings)

			{ 640, 480, 25175, 96, 16, 48, 2, 11, 31,

				OMAPDSS_SIG_ACTIVE_LOW, OMAPDSS_SIG_ACTIVE_LOW,

				false,

			};



	DSSDBG("hdmi_panel_probe x_res= %d y_res = %d\n",

drivers/video/omap2/dss/venc.c

+4 −0
Original line number Diff line number Diff line
@@ -272,6 +272,8 @@ const struct omap_video_timings omap_dss_pal_timings = { 
	.vsw		= 5,

	.vfp		= 5,

	.vbp		= 41,



	.interlace	= true,

};

EXPORT_SYMBOL(omap_dss_pal_timings);
@@ -285,6 +287,8 @@ const struct omap_video_timings omap_dss_ntsc_timings = { 
	.vsw		= 6,

	.vfp		= 6,

	.vbp		= 31,



	.interlace	= true,

};

EXPORT_SYMBOL(omap_dss_ntsc_timings);

include/video/omapdss.h

+2 −0
Original line number Diff line number Diff line
@@ -344,6 +344,8 @@ struct omap_video_timings { 
	enum omap_dss_signal_level vsync_level;

	/* Hsync logic level */

	enum omap_dss_signal_level hsync_level;

	/* Interlaced or Progressive timings */

	bool interlace;

	/* Pixel clock edge to drive LCD data */

	enum omap_dss_signal_edge data_pclk_edge;

	/* Data enable logic level */

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