Commit 23c73b24 authored by Dave Airlie's avatar Dave Airlie
Browse files

Merge branch 'drm-next-3.15' of git://people.freedesktop.org/~deathsimple/linux into drm-next 

this is the third pull request for 3.15 radeon changes. Highlights this time:
- More DP work from Alex, especially making use of the new DP aux helpers
- Marek's 1D and linear tiling fixes for CIK

* 'drm-next-3.15' of git://people.freedesktop.org/~deathsimple/linux:
  drm/radeon: set PIPE_CONFIG for 1D and linear tiling modes on CIK
  drm/radeon: use drm_dp_dpcd_read_link_status()
  drm/radeon: use the new drm helpers for dp aux
  drm/dp: make aux retries less chatty
  drm/radeon: clarify special handling in i2c over aux
  drm/radeon/atom: rework encoder enable/disable sequence
  drm/radeon/dp: move sink power control to a separate function
  drm/radeon/dp: use i2c_get_adapdata rather than casting
parents 63ac07cd 020ff546

drivers/gpu/drm/drm_dp_helper.c

+2 −2
Original line number Diff line number Diff line
@@ -402,7 +402,7 @@ static int drm_dp_dpcd_access(struct drm_dp_aux *aux, u8 request, 
		}

	}



	DRM_ERROR("too many retries, giving up\n");

	DRM_DEBUG_KMS("too many retries, giving up\n");

	return -EIO;

}
@@ -656,7 +656,7 @@ static int drm_dp_i2c_do_msg(struct drm_dp_aux *aux, struct drm_dp_aux_msg *msg) 
		}

	}



	DRM_ERROR("too many retries, giving up\n");

	DRM_DEBUG_KMS("too many retries, giving up\n");

	return -EREMOTEIO;

}

drivers/gpu/drm/radeon/atombios_dp.c

+122 −146
Original line number Diff line number Diff line
@@ -142,101 +142,69 @@ static int radeon_process_aux_ch(struct radeon_i2c_chan *chan, 
	return recv_bytes;

}



static int radeon_dp_aux_native_write(struct radeon_connector *radeon_connector,

				      u16 address, u8 *send, u8 send_bytes, u8 delay)

{

	struct radeon_connector_atom_dig *dig_connector = radeon_connector->con_priv;

	int ret;

	u8 msg[20];

	int msg_bytes = send_bytes + 4;

	u8 ack;

	unsigned retry;



	if (send_bytes > 16)

		return -1;



	msg[0] = address;

	msg[1] = address >> 8;

	msg[2] = DP_AUX_NATIVE_WRITE << 4;

	msg[3] = (msg_bytes << 4) | (send_bytes - 1);

	memcpy(&msg[4], send, send_bytes);



	for (retry = 0; retry < 7; retry++) {

		ret = radeon_process_aux_ch(dig_connector->dp_i2c_bus,

					    msg, msg_bytes, NULL, 0, delay, &ack);

		if (ret == -EBUSY)

			continue;

		else if (ret < 0)

			return ret;

		ack >>= 4;

		if ((ack & DP_AUX_NATIVE_REPLY_MASK) == DP_AUX_NATIVE_REPLY_ACK)

			return send_bytes;

		else if ((ack & DP_AUX_NATIVE_REPLY_MASK) == DP_AUX_NATIVE_REPLY_DEFER)

			usleep_range(400, 500);

		else

			return -EIO;

	}

#define HEADER_SIZE 4



	return -EIO;

}



static int radeon_dp_aux_native_read(struct radeon_connector *radeon_connector,

				     u16 address, u8 *recv, int recv_bytes, u8 delay)

static ssize_t

radeon_dp_aux_transfer(struct drm_dp_aux *aux, struct drm_dp_aux_msg *msg)

{

	struct radeon_connector_atom_dig *dig_connector = radeon_connector->con_priv;

	u8 msg[4];

	int msg_bytes = 4;

	u8 ack;

	struct radeon_i2c_chan *chan =

		container_of(aux, struct radeon_i2c_chan, aux);

	int ret;

	unsigned retry;



	msg[0] = address;

	msg[1] = address >> 8;

	msg[2] = DP_AUX_NATIVE_READ << 4;

	msg[3] = (msg_bytes << 4) | (recv_bytes - 1);



	for (retry = 0; retry < 7; retry++) {

		ret = radeon_process_aux_ch(dig_connector->dp_i2c_bus,

					    msg, msg_bytes, recv, recv_bytes, delay, &ack);

		if (ret == -EBUSY)

			continue;

		else if (ret < 0)

			return ret;

		ack >>= 4;

		if ((ack & DP_AUX_NATIVE_REPLY_MASK) == DP_AUX_NATIVE_REPLY_ACK)

			return ret;

		else if ((ack & DP_AUX_NATIVE_REPLY_MASK) == DP_AUX_NATIVE_REPLY_DEFER)

			usleep_range(400, 500);

		else if (ret == 0)

			return -EPROTO;

		else

			return -EIO;

	u8 tx_buf[20];

	size_t tx_size;

	u8 ack, delay = 0;



	if (WARN_ON(msg->size > 16))

		return -E2BIG;



	tx_buf[0] = msg->address & 0xff;

	tx_buf[1] = msg->address >> 8;

	tx_buf[2] = msg->request << 4;

	tx_buf[3] = msg->size - 1;



	switch (msg->request & ~DP_AUX_I2C_MOT) {

	case DP_AUX_NATIVE_WRITE:

	case DP_AUX_I2C_WRITE:

		tx_size = HEADER_SIZE + msg->size;

		tx_buf[3] |= tx_size << 4;

		memcpy(tx_buf + HEADER_SIZE, msg->buffer, msg->size);

		ret = radeon_process_aux_ch(chan,

					    tx_buf, tx_size, NULL, 0, delay, &ack);

		if (ret >= 0)

			/* Return payload size. */

			ret = msg->size;

		break;

	case DP_AUX_NATIVE_READ:

	case DP_AUX_I2C_READ:

		tx_size = HEADER_SIZE;

		tx_buf[3] |= tx_size << 4;

		ret = radeon_process_aux_ch(chan,

					    tx_buf, tx_size, msg->buffer, msg->size, delay, &ack);

		break;

	default:

		ret = -EINVAL;

		break;

	}



	return -EIO;

}

	if (ret > 0)

		msg->reply = ack >> 4;



static void radeon_write_dpcd_reg(struct radeon_connector *radeon_connector,

				 u16 reg, u8 val)

{

	radeon_dp_aux_native_write(radeon_connector, reg, &val, 1, 0);

	return ret;

}



static u8 radeon_read_dpcd_reg(struct radeon_connector *radeon_connector,

			       u16 reg)

void radeon_dp_aux_init(struct radeon_connector *radeon_connector)

{

	u8 val = 0;



	radeon_dp_aux_native_read(radeon_connector, reg, &val, 1, 0);

	struct radeon_connector_atom_dig *dig_connector = radeon_connector->con_priv;



	return val;

	dig_connector->dp_i2c_bus->aux.dev = radeon_connector->base.kdev;

	dig_connector->dp_i2c_bus->aux.transfer = radeon_dp_aux_transfer;

}



int radeon_dp_i2c_aux_ch(struct i2c_adapter *adapter, int mode,

			 u8 write_byte, u8 *read_byte)

{

	struct i2c_algo_dp_aux_data *algo_data = adapter->algo_data;

	struct radeon_i2c_chan *auxch = (struct radeon_i2c_chan *)adapter;

	struct radeon_i2c_chan *auxch = i2c_get_adapdata(adapter);

	u16 address = algo_data->address;

	u8 msg[5];

	u8 reply[2];
@@ -246,34 +214,30 @@ int radeon_dp_i2c_aux_ch(struct i2c_adapter *adapter, int mode, 
	int ret;

	u8 ack;



	/* Set up the command byte */

	if (mode & MODE_I2C_READ)

		msg[2] = DP_AUX_I2C_READ << 4;

	else

		msg[2] = DP_AUX_I2C_WRITE << 4;



	if (!(mode & MODE_I2C_STOP))

		msg[2] |= DP_AUX_I2C_MOT << 4;



	/* Set up the address */

	msg[0] = address;

	msg[1] = address >> 8;



	switch (mode) {

	case MODE_I2C_WRITE:

	/* Set up the command byte */

	if (mode & MODE_I2C_READ) {

		msg[2] = DP_AUX_I2C_READ << 4;

		msg_bytes = 4;

		msg[3] = msg_bytes << 4;

	} else {

		msg[2] = DP_AUX_I2C_WRITE << 4;

		msg_bytes = 5;

		msg[3] = msg_bytes << 4;

		msg[4] = write_byte;

		break;

	case MODE_I2C_READ:

		msg_bytes = 4;

		msg[3] = msg_bytes << 4;

		break;

	default:

		msg_bytes = 4;

		msg[3] = 3 << 4;

		break;

	}



	/* special handling for start/stop */

	if (mode & (MODE_I2C_START | MODE_I2C_STOP))

		msg[3] = 3 << 4;



	/* Set MOT bit for all but stop */

	if ((mode & MODE_I2C_STOP) == 0)

		msg[2] |= DP_AUX_I2C_MOT << 4;



	for (retry = 0; retry < 7; retry++) {

		ret = radeon_process_aux_ch(auxch,

					    msg, msg_bytes, reply, reply_bytes, 0, &ack);
@@ -472,11 +436,11 @@ static void radeon_dp_probe_oui(struct radeon_connector *radeon_connector) 
	if (!(dig_connector->dpcd[DP_DOWN_STREAM_PORT_COUNT] & DP_OUI_SUPPORT))

		return;



	if (radeon_dp_aux_native_read(radeon_connector, DP_SINK_OUI, buf, 3, 0))

	if (drm_dp_dpcd_read(&dig_connector->dp_i2c_bus->aux, DP_SINK_OUI, buf, 3))

		DRM_DEBUG_KMS("Sink OUI: %02hx%02hx%02hx\n",

			      buf[0], buf[1], buf[2]);



	if (radeon_dp_aux_native_read(radeon_connector, DP_BRANCH_OUI, buf, 3, 0))

	if (drm_dp_dpcd_read(&dig_connector->dp_i2c_bus->aux, DP_BRANCH_OUI, buf, 3))

		DRM_DEBUG_KMS("Branch OUI: %02hx%02hx%02hx\n",

			      buf[0], buf[1], buf[2]);

}
@@ -487,8 +451,8 @@ bool radeon_dp_getdpcd(struct radeon_connector *radeon_connector) 
	u8 msg[DP_DPCD_SIZE];

	int ret, i;



	ret = radeon_dp_aux_native_read(radeon_connector, DP_DPCD_REV, msg,

					DP_DPCD_SIZE, 0);

	ret = drm_dp_dpcd_read(&dig_connector->dp_i2c_bus->aux, DP_DPCD_REV, msg,

			       DP_DPCD_SIZE);

	if (ret > 0) {

		memcpy(dig_connector->dpcd, msg, DP_DPCD_SIZE);

		DRM_DEBUG_KMS("DPCD: ");
@@ -510,6 +474,7 @@ int radeon_dp_get_panel_mode(struct drm_encoder *encoder, 
	struct drm_device *dev = encoder->dev;

	struct radeon_device *rdev = dev->dev_private;

	struct radeon_connector *radeon_connector = to_radeon_connector(connector);

	struct radeon_connector_atom_dig *dig_connector;

	int panel_mode = DP_PANEL_MODE_EXTERNAL_DP_MODE;

	u16 dp_bridge = radeon_connector_encoder_get_dp_bridge_encoder_id(connector);

	u8 tmp;
@@ -517,9 +482,15 @@ int radeon_dp_get_panel_mode(struct drm_encoder *encoder, 
	if (!ASIC_IS_DCE4(rdev))

		return panel_mode;



	if (!radeon_connector->con_priv)

		return panel_mode;



	dig_connector = radeon_connector->con_priv;



	if (dp_bridge != ENCODER_OBJECT_ID_NONE) {

		/* DP bridge chips */

		tmp = radeon_read_dpcd_reg(radeon_connector, DP_EDP_CONFIGURATION_CAP);

		drm_dp_dpcd_readb(&dig_connector->dp_i2c_bus->aux,

				  DP_EDP_CONFIGURATION_CAP, &tmp);

		if (tmp & 1)

			panel_mode = DP_PANEL_MODE_INTERNAL_DP2_MODE;

		else if ((dp_bridge == ENCODER_OBJECT_ID_NUTMEG) ||
@@ -529,7 +500,8 @@ int radeon_dp_get_panel_mode(struct drm_encoder *encoder, 
			panel_mode = DP_PANEL_MODE_EXTERNAL_DP_MODE;

	} else if (connector->connector_type == DRM_MODE_CONNECTOR_eDP) {

		/* eDP */

		tmp = radeon_read_dpcd_reg(radeon_connector, DP_EDP_CONFIGURATION_CAP);

		drm_dp_dpcd_readb(&dig_connector->dp_i2c_bus->aux,

				  DP_EDP_CONFIGURATION_CAP, &tmp);

		if (tmp & 1)

			panel_mode = DP_PANEL_MODE_INTERNAL_DP2_MODE;

	}
@@ -577,37 +549,42 @@ int radeon_dp_mode_valid_helper(struct drm_connector *connector, 
	return MODE_OK;

}



static bool radeon_dp_get_link_status(struct radeon_connector *radeon_connector,

				      u8 link_status[DP_LINK_STATUS_SIZE])

{

	int ret;

	ret = radeon_dp_aux_native_read(radeon_connector, DP_LANE0_1_STATUS,

					link_status, DP_LINK_STATUS_SIZE, 100);

	if (ret <= 0) {

		return false;

	}



	DRM_DEBUG_KMS("link status %6ph\n", link_status);

	return true;

}



bool radeon_dp_needs_link_train(struct radeon_connector *radeon_connector)

{

	u8 link_status[DP_LINK_STATUS_SIZE];

	struct radeon_connector_atom_dig *dig = radeon_connector->con_priv;



	if (!radeon_dp_get_link_status(radeon_connector, link_status))

	if (drm_dp_dpcd_read_link_status(&dig->dp_i2c_bus->aux, link_status) <= 0)

		return false;

	if (drm_dp_channel_eq_ok(link_status, dig->dp_lane_count))

		return false;

	return true;

}



void radeon_dp_set_rx_power_state(struct drm_connector *connector,

				  u8 power_state)

{

	struct radeon_connector *radeon_connector = to_radeon_connector(connector);

	struct radeon_connector_atom_dig *dig_connector;



	if (!radeon_connector->con_priv)

		return;



	dig_connector = radeon_connector->con_priv;



	/* power up/down the sink */

	if (dig_connector->dpcd[0] >= 0x11) {

		drm_dp_dpcd_writeb(&dig_connector->dp_i2c_bus->aux,

				   DP_SET_POWER, power_state);

		usleep_range(1000, 2000);

	}

}





struct radeon_dp_link_train_info {

	struct radeon_device *rdev;

	struct drm_encoder *encoder;

	struct drm_connector *connector;

	struct radeon_connector *radeon_connector;

	int enc_id;

	int dp_clock;

	int dp_lane_count;
@@ -617,6 +594,7 @@ struct radeon_dp_link_train_info { 
	u8 link_status[DP_LINK_STATUS_SIZE];

	u8 tries;

	bool use_dpencoder;

	struct drm_dp_aux *aux;

};



static void radeon_dp_update_vs_emph(struct radeon_dp_link_train_info *dp_info)
@@ -627,8 +605,8 @@ static void radeon_dp_update_vs_emph(struct radeon_dp_link_train_info *dp_info) 
				       0, dp_info->train_set[0]); /* sets all lanes at once */



	/* set the vs/emph on the sink */

	radeon_dp_aux_native_write(dp_info->radeon_connector, DP_TRAINING_LANE0_SET,

				   dp_info->train_set, dp_info->dp_lane_count, 0);

	drm_dp_dpcd_write(dp_info->aux, DP_TRAINING_LANE0_SET,

			  dp_info->train_set, dp_info->dp_lane_count);

}



static void radeon_dp_set_tp(struct radeon_dp_link_train_info *dp_info, int tp)
@@ -663,7 +641,7 @@ static void radeon_dp_set_tp(struct radeon_dp_link_train_info *dp_info, int tp) 
	}



	/* enable training pattern on the sink */

	radeon_write_dpcd_reg(dp_info->radeon_connector, DP_TRAINING_PATTERN_SET, tp);

	drm_dp_dpcd_writeb(dp_info->aux, DP_TRAINING_PATTERN_SET, tp);

}



static int radeon_dp_link_train_init(struct radeon_dp_link_train_info *dp_info)
@@ -673,34 +651,30 @@ static int radeon_dp_link_train_init(struct radeon_dp_link_train_info *dp_info) 
	u8 tmp;



	/* power up the sink */

	if (dp_info->dpcd[0] >= 0x11) {

		radeon_write_dpcd_reg(dp_info->radeon_connector,

				      DP_SET_POWER, DP_SET_POWER_D0);

		usleep_range(1000, 2000);

	}

	radeon_dp_set_rx_power_state(dp_info->connector, DP_SET_POWER_D0);



	/* possibly enable downspread on the sink */

	if (dp_info->dpcd[3] & 0x1)

		radeon_write_dpcd_reg(dp_info->radeon_connector,

		drm_dp_dpcd_writeb(dp_info->aux,

				   DP_DOWNSPREAD_CTRL, DP_SPREAD_AMP_0_5);

	else

		radeon_write_dpcd_reg(dp_info->radeon_connector,

		drm_dp_dpcd_writeb(dp_info->aux,

				   DP_DOWNSPREAD_CTRL, 0);



	if ((dp_info->connector->connector_type == DRM_MODE_CONNECTOR_eDP) &&

	    (dig->panel_mode == DP_PANEL_MODE_INTERNAL_DP2_MODE)) {

		radeon_write_dpcd_reg(dp_info->radeon_connector, DP_EDP_CONFIGURATION_SET, 1);

		drm_dp_dpcd_writeb(dp_info->aux, DP_EDP_CONFIGURATION_SET, 1);

	}



	/* set the lane count on the sink */

	tmp = dp_info->dp_lane_count;

	if (drm_dp_enhanced_frame_cap(dp_info->dpcd))

		tmp |= DP_LANE_COUNT_ENHANCED_FRAME_EN;

	radeon_write_dpcd_reg(dp_info->radeon_connector, DP_LANE_COUNT_SET, tmp);

	drm_dp_dpcd_writeb(dp_info->aux, DP_LANE_COUNT_SET, tmp);



	/* set the link rate on the sink */

	tmp = drm_dp_link_rate_to_bw_code(dp_info->dp_clock);

	radeon_write_dpcd_reg(dp_info->radeon_connector, DP_LINK_BW_SET, tmp);

	drm_dp_dpcd_writeb(dp_info->aux, DP_LINK_BW_SET, tmp);



	/* start training on the source */

	if (ASIC_IS_DCE4(dp_info->rdev) || !dp_info->use_dpencoder)
@@ -711,7 +685,7 @@ static int radeon_dp_link_train_init(struct radeon_dp_link_train_info *dp_info) 
					  dp_info->dp_clock, dp_info->enc_id, 0);



	/* disable the training pattern on the sink */

	radeon_write_dpcd_reg(dp_info->radeon_connector,

	drm_dp_dpcd_writeb(dp_info->aux,

			   DP_TRAINING_PATTERN_SET,

			   DP_TRAINING_PATTERN_DISABLE);
@@ -723,7 +697,7 @@ static int radeon_dp_link_train_finish(struct radeon_dp_link_train_info *dp_info 
	udelay(400);



	/* disable the training pattern on the sink */

	radeon_write_dpcd_reg(dp_info->radeon_connector,

	drm_dp_dpcd_writeb(dp_info->aux,

			   DP_TRAINING_PATTERN_SET,

			   DP_TRAINING_PATTERN_DISABLE);
@@ -757,7 +731,8 @@ static int radeon_dp_link_train_cr(struct radeon_dp_link_train_info *dp_info) 
	while (1) {

		drm_dp_link_train_clock_recovery_delay(dp_info->dpcd);



		if (!radeon_dp_get_link_status(dp_info->radeon_connector, dp_info->link_status)) {

		if (drm_dp_dpcd_read_link_status(dp_info->aux,

						 dp_info->link_status) <= 0) {

			DRM_ERROR("displayport link status failed\n");

			break;

		}
@@ -819,7 +794,8 @@ static int radeon_dp_link_train_ce(struct radeon_dp_link_train_info *dp_info) 
	while (1) {

		drm_dp_link_train_channel_eq_delay(dp_info->dpcd);



		if (!radeon_dp_get_link_status(dp_info->radeon_connector, dp_info->link_status)) {

		if (drm_dp_dpcd_read_link_status(dp_info->aux,

						 dp_info->link_status) <= 0) {

			DRM_ERROR("displayport link status failed\n");

			break;

		}
@@ -902,7 +878,7 @@ void radeon_dp_link_train(struct drm_encoder *encoder, 
	else

		dp_info.enc_id |= ATOM_DP_CONFIG_LINK_A;



	tmp = radeon_read_dpcd_reg(radeon_connector, DP_MAX_LANE_COUNT);

	drm_dp_dpcd_readb(&dig_connector->dp_i2c_bus->aux, DP_MAX_LANE_COUNT, &tmp);

	if (ASIC_IS_DCE5(rdev) && (tmp & DP_TPS3_SUPPORTED))

		dp_info.tp3_supported = true;

	else
@@ -912,9 +888,9 @@ void radeon_dp_link_train(struct drm_encoder *encoder, 
	dp_info.rdev = rdev;

	dp_info.encoder = encoder;

	dp_info.connector = connector;

	dp_info.radeon_connector = radeon_connector;

	dp_info.dp_lane_count = dig_connector->dp_lane_count;

	dp_info.dp_clock = dig_connector->dp_clock;

	dp_info.aux = &dig_connector->dp_i2c_bus->aux;



	if (radeon_dp_link_train_init(&dp_info))

		goto done;

drivers/gpu/drm/radeon/atombios_encoders.c

+34 −48
Original line number Diff line number Diff line
@@ -1633,10 +1633,16 @@ radeon_atom_encoder_dpms_dig(struct drm_encoder *encoder, int mode) 
	struct drm_connector *connector = radeon_get_connector_for_encoder(encoder);

	struct radeon_connector *radeon_connector = NULL;

	struct radeon_connector_atom_dig *radeon_dig_connector = NULL;

	bool travis_quirk = false;



	if (connector) {

		radeon_connector = to_radeon_connector(connector);

		radeon_dig_connector = radeon_connector->con_priv;

		if ((radeon_connector_encoder_get_dp_bridge_encoder_id(connector) ==

		     ENCODER_OBJECT_ID_TRAVIS) &&

		    (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT)) &&

		    !ASIC_IS_DCE5(rdev))

			travis_quirk = true;

	}



	switch (mode) {
@@ -1657,17 +1663,13 @@ radeon_atom_encoder_dpms_dig(struct drm_encoder *encoder, int mode) 
					atombios_external_encoder_setup(encoder, ext_encoder,

									EXTERNAL_ENCODER_ACTION_V3_ENCODER_SETUP);

			}

			atombios_dig_transmitter_setup(encoder, ATOM_TRANSMITTER_ACTION_ENABLE, 0, 0);

		} else if (ASIC_IS_DCE4(rdev)) {

			/* setup and enable the encoder */

			atombios_dig_encoder_setup(encoder, ATOM_ENCODER_CMD_SETUP, 0);

			/* enable the transmitter */

			atombios_dig_transmitter_setup(encoder, ATOM_TRANSMITTER_ACTION_ENABLE, 0, 0);

		} else {

			/* setup and enable the encoder and transmitter */

			atombios_dig_encoder_setup(encoder, ATOM_ENABLE, 0);

			atombios_dig_transmitter_setup(encoder, ATOM_TRANSMITTER_ACTION_SETUP, 0, 0);

			atombios_dig_transmitter_setup(encoder, ATOM_TRANSMITTER_ACTION_ENABLE, 0, 0);

		}

		if (ENCODER_MODE_IS_DP(atombios_get_encoder_mode(encoder)) && connector) {

			if (connector->connector_type == DRM_MODE_CONNECTOR_eDP) {
@@ -1675,68 +1677,56 @@ radeon_atom_encoder_dpms_dig(struct drm_encoder *encoder, int mode) 
							     ATOM_TRANSMITTER_ACTION_POWER_ON);

				radeon_dig_connector->edp_on = true;

			}

		}

		/* enable the transmitter */

		atombios_dig_transmitter_setup(encoder, ATOM_TRANSMITTER_ACTION_ENABLE, 0, 0);

		if (ENCODER_MODE_IS_DP(atombios_get_encoder_mode(encoder)) && connector) {

			/* DP_SET_POWER_D0 is set in radeon_dp_link_train */

			radeon_dp_link_train(encoder, connector);

			if (ASIC_IS_DCE4(rdev))

				atombios_dig_encoder_setup(encoder, ATOM_ENCODER_CMD_DP_VIDEO_ON, 0);

		}

		if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT))

			atombios_dig_transmitter_setup(encoder, ATOM_TRANSMITTER_ACTION_LCD_BLON, 0, 0);

			atombios_dig_transmitter_setup(encoder,

						       ATOM_TRANSMITTER_ACTION_LCD_BLON, 0, 0);

		if (ext_encoder)

			atombios_external_encoder_setup(encoder, ext_encoder, ATOM_ENABLE);

		break;

	case DRM_MODE_DPMS_STANDBY:

	case DRM_MODE_DPMS_SUSPEND:

	case DRM_MODE_DPMS_OFF:

		if (ASIC_IS_DCE4(rdev)) {

			if (ENCODER_MODE_IS_DP(atombios_get_encoder_mode(encoder)) && connector)

				atombios_dig_encoder_setup(encoder, ATOM_ENCODER_CMD_DP_VIDEO_OFF, 0);

		}

		if (ext_encoder)

			atombios_external_encoder_setup(encoder, ext_encoder, ATOM_DISABLE);

		if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT))

			atombios_dig_transmitter_setup(encoder,

						       ATOM_TRANSMITTER_ACTION_LCD_BLOFF, 0, 0);



		if (ENCODER_MODE_IS_DP(atombios_get_encoder_mode(encoder)) &&

		    connector && !travis_quirk)

			radeon_dp_set_rx_power_state(connector, DP_SET_POWER_D3);

		if (ASIC_IS_DCE4(rdev)) {

			/* disable the transmitter */

			atombios_dig_transmitter_setup(encoder, ATOM_TRANSMITTER_ACTION_DISABLE, 0, 0);

			atombios_dig_transmitter_setup(encoder,

						       ATOM_TRANSMITTER_ACTION_DISABLE, 0, 0);

		} else {

			/* disable the encoder and transmitter */

			atombios_dig_transmitter_setup(encoder, ATOM_TRANSMITTER_ACTION_DISABLE, 0, 0);

			atombios_dig_transmitter_setup(encoder,

						       ATOM_TRANSMITTER_ACTION_DISABLE, 0, 0);

			atombios_dig_encoder_setup(encoder, ATOM_DISABLE, 0);

		}

		if (ENCODER_MODE_IS_DP(atombios_get_encoder_mode(encoder)) && connector) {

			if (ASIC_IS_DCE4(rdev))

				atombios_dig_encoder_setup(encoder, ATOM_ENCODER_CMD_DP_VIDEO_OFF, 0);

			if (travis_quirk)

				radeon_dp_set_rx_power_state(connector, DP_SET_POWER_D3);

			if (connector->connector_type == DRM_MODE_CONNECTOR_eDP) {

				atombios_set_edp_panel_power(connector,

							     ATOM_TRANSMITTER_ACTION_POWER_OFF);

				radeon_dig_connector->edp_on = false;

			}

		}

		if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT))

			atombios_dig_transmitter_setup(encoder, ATOM_TRANSMITTER_ACTION_LCD_BLOFF, 0, 0);

		break;

	}

}



static void

radeon_atom_encoder_dpms_ext(struct drm_encoder *encoder,

			     struct drm_encoder *ext_encoder,

			     int mode)

{

	struct drm_device *dev = encoder->dev;

	struct radeon_device *rdev = dev->dev_private;



	switch (mode) {

	case DRM_MODE_DPMS_ON:

	default:

		if (ASIC_IS_DCE41(rdev) || ASIC_IS_DCE61(rdev)) {

			atombios_external_encoder_setup(encoder, ext_encoder,

							EXTERNAL_ENCODER_ACTION_V3_ENABLE_OUTPUT);

			atombios_external_encoder_setup(encoder, ext_encoder,

							EXTERNAL_ENCODER_ACTION_V3_ENCODER_BLANKING_OFF);

		} else

			atombios_external_encoder_setup(encoder, ext_encoder, ATOM_ENABLE);

		break;

	case DRM_MODE_DPMS_STANDBY:

	case DRM_MODE_DPMS_SUSPEND:

	case DRM_MODE_DPMS_OFF:

		if (ASIC_IS_DCE41(rdev) || ASIC_IS_DCE61(rdev)) {

			atombios_external_encoder_setup(encoder, ext_encoder,

							EXTERNAL_ENCODER_ACTION_V3_ENCODER_BLANKING);

			atombios_external_encoder_setup(encoder, ext_encoder,

							EXTERNAL_ENCODER_ACTION_V3_DISABLE_OUTPUT);

		} else

			atombios_external_encoder_setup(encoder, ext_encoder, ATOM_DISABLE);

		break;

	}

}
@@ -1747,7 +1737,6 @@ radeon_atom_encoder_dpms(struct drm_encoder *encoder, int mode) 
	struct drm_device *dev = encoder->dev;

	struct radeon_device *rdev = dev->dev_private;

	struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);

	struct drm_encoder *ext_encoder = radeon_get_external_encoder(encoder);



	DRM_DEBUG_KMS("encoder dpms %d to mode %d, devices %08x, active_devices %08x\n",

		  radeon_encoder->encoder_id, mode, radeon_encoder->devices,
@@ -1807,9 +1796,6 @@ radeon_atom_encoder_dpms(struct drm_encoder *encoder, int mode) 
		return;

	}



	if (ext_encoder)

		radeon_atom_encoder_dpms_ext(encoder, ext_encoder, mode);



	radeon_atombios_encoder_dpms_scratch_regs(encoder, (mode == DRM_MODE_DPMS_ON) ? true : false);



}

drivers/gpu/drm/radeon/cik.c

+24 −3
Original line number Diff line number Diff line
@@ -2029,6 +2029,7 @@ static void cik_tiling_mode_table_init(struct radeon_device *rdev) 
				break;

			case 5:

				gb_tile_moden = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |

						 PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) |

						 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));

				break;

			case 6:
@@ -2049,6 +2050,7 @@ static void cik_tiling_mode_table_init(struct radeon_device *rdev) 
				break;

			case 9:

				gb_tile_moden = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |

						 PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) |

						 MICRO_TILE_MODE_NEW(ADDR_SURF_DISPLAY_MICRO_TILING));

				break;

			case 10:
@@ -2071,6 +2073,7 @@ static void cik_tiling_mode_table_init(struct radeon_device *rdev) 
				break;

			case 13:

				gb_tile_moden = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |

						 PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) |

						 MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING));

				break;

			case 14:
@@ -2093,6 +2096,7 @@ static void cik_tiling_mode_table_init(struct radeon_device *rdev) 
				break;

			case 27:

				gb_tile_moden = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |

						 PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) |

						 MICRO_TILE_MODE_NEW(ADDR_SURF_ROTATED_MICRO_TILING));

				break;

			case 28:
@@ -2247,6 +2251,7 @@ static void cik_tiling_mode_table_init(struct radeon_device *rdev) 
				break;

			case 5:

				gb_tile_moden = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |

						 PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16) |

						 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));

				break;

			case 6:
@@ -2267,6 +2272,7 @@ static void cik_tiling_mode_table_init(struct radeon_device *rdev) 
				break;

			case 9:

				gb_tile_moden = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |

						 PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16) |

						 MICRO_TILE_MODE_NEW(ADDR_SURF_DISPLAY_MICRO_TILING));

				break;

			case 10:
@@ -2289,6 +2295,7 @@ static void cik_tiling_mode_table_init(struct radeon_device *rdev) 
				break;

			case 13:

				gb_tile_moden = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |

						 PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16) |

						 MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING));

				break;

			case 14:
@@ -2311,6 +2318,7 @@ static void cik_tiling_mode_table_init(struct radeon_device *rdev) 
				break;

			case 27:

				gb_tile_moden = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |

						 PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16) |

						 MICRO_TILE_MODE_NEW(ADDR_SURF_ROTATED_MICRO_TILING));

				break;

			case 28:
@@ -2467,6 +2475,7 @@ static void cik_tiling_mode_table_init(struct radeon_device *rdev) 
					break;

				case 5:

					gb_tile_moden = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |

							 PIPE_CONFIG(ADDR_SURF_P4_16x16) |

							 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));

					break;

				case 6:
@@ -2487,6 +2496,7 @@ static void cik_tiling_mode_table_init(struct radeon_device *rdev) 
					break;

				case 9:

					gb_tile_moden = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |

							 PIPE_CONFIG(ADDR_SURF_P4_16x16) |

							 MICRO_TILE_MODE_NEW(ADDR_SURF_DISPLAY_MICRO_TILING));

					break;

				case 10:
@@ -2509,6 +2519,7 @@ static void cik_tiling_mode_table_init(struct radeon_device *rdev) 
					break;

				case 13:

					gb_tile_moden = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |

							 PIPE_CONFIG(ADDR_SURF_P4_16x16) |

							 MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING));

					break;

				case 14:
@@ -2531,6 +2542,7 @@ static void cik_tiling_mode_table_init(struct radeon_device *rdev) 
					break;

				case 27:

					gb_tile_moden = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |

							 PIPE_CONFIG(ADDR_SURF_P4_16x16) |

							 MICRO_TILE_MODE_NEW(ADDR_SURF_ROTATED_MICRO_TILING));

					break;

				case 28:
@@ -2593,6 +2605,7 @@ static void cik_tiling_mode_table_init(struct radeon_device *rdev) 
					break;

				case 5:

					gb_tile_moden = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |

							 PIPE_CONFIG(ADDR_SURF_P4_8x16) |

							 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));

					break;

				case 6:
@@ -2613,6 +2626,7 @@ static void cik_tiling_mode_table_init(struct radeon_device *rdev) 
					break;

				case 9:

					gb_tile_moden = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |

							 PIPE_CONFIG(ADDR_SURF_P4_8x16) |

							 MICRO_TILE_MODE_NEW(ADDR_SURF_DISPLAY_MICRO_TILING));

					break;

				case 10:
@@ -2635,6 +2649,7 @@ static void cik_tiling_mode_table_init(struct radeon_device *rdev) 
					break;

				case 13:

					gb_tile_moden = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |

							 PIPE_CONFIG(ADDR_SURF_P4_8x16) |

							 MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING));

					break;

				case 14:
@@ -2657,6 +2672,7 @@ static void cik_tiling_mode_table_init(struct radeon_device *rdev) 
					break;

				case 27:

					gb_tile_moden = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |

							 PIPE_CONFIG(ADDR_SURF_P4_8x16) |

							 MICRO_TILE_MODE_NEW(ADDR_SURF_ROTATED_MICRO_TILING));

					break;

				case 28:
@@ -2813,6 +2829,7 @@ static void cik_tiling_mode_table_init(struct radeon_device *rdev) 
				break;

			case 5:

				gb_tile_moden = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |

						 PIPE_CONFIG(ADDR_SURF_P2) |

						 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));

				break;

			case 6:
@@ -2828,11 +2845,13 @@ static void cik_tiling_mode_table_init(struct radeon_device *rdev) 
						 TILE_SPLIT(split_equal_to_row_size));

				break;

			case 8:

				gb_tile_moden = ARRAY_MODE(ARRAY_LINEAR_ALIGNED);

				gb_tile_moden = ARRAY_MODE(ARRAY_LINEAR_ALIGNED) |

						PIPE_CONFIG(ADDR_SURF_P2);

				break;

			case 9:

				gb_tile_moden = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |

						 MICRO_TILE_MODE_NEW(ADDR_SURF_DISPLAY_MICRO_TILING));

						 MICRO_TILE_MODE_NEW(ADDR_SURF_DISPLAY_MICRO_TILING) |

						 PIPE_CONFIG(ADDR_SURF_P2));

				break;

			case 10:

				gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
@@ -2854,6 +2873,7 @@ static void cik_tiling_mode_table_init(struct radeon_device *rdev) 
				break;

			case 13:

				gb_tile_moden = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |

						 PIPE_CONFIG(ADDR_SURF_P2) |

						 MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING));

				break;

			case 14:
@@ -2876,7 +2896,8 @@ static void cik_tiling_mode_table_init(struct radeon_device *rdev) 
				break;

			case 27:

				gb_tile_moden = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |

						 MICRO_TILE_MODE_NEW(ADDR_SURF_ROTATED_MICRO_TILING));

						 MICRO_TILE_MODE_NEW(ADDR_SURF_ROTATED_MICRO_TILING) |

						 PIPE_CONFIG(ADDR_SURF_P2));

				break;

			case 28:

				gb_tile_moden = (ARRAY_MODE(ARRAY_PRT_2D_TILED_THIN1) |

drivers/gpu/drm/radeon/radeon_connectors.c

+14 −3

File changed.

Preview size limit exceeded, changes collapsed.

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