Unverified Commit 23b89e1d authored by Jerome Brunet's avatar Jerome Brunet Committed by Mark Brown
Browse files

ASoC: meson: axg-fifo: improve depth handling 



Let the fifo driver parse the fifo depth from DT. Eventually all DT should
have this property. Until it is actually the case, default to 256 bytes if
the property is missing. 256 bytes is the size of the smallest fifo on the
supported SoCs.

On the supported SoC, fifo A is usually bigger than the other ones.  With
depth known, we can improve the usage of the fifo and adapt the setup of
request threshold.

Signed-off-by: default avatarJerome Brunet <jbrunet@baylibre.com>
Link: https://lore.kernel.org/r/20191218172420.1199117-4-jbrunet@baylibre.com


Signed-off-by: default avatarMark Brown <broonie@kernel.org>
parent 864cee90

sound/soc/meson/axg-fifo.c

+17 −2
Original line number Diff line number Diff line
@@ -132,8 +132,7 @@ int axg_fifo_pcm_hw_params(struct snd_soc_component *component, 
	 * - Half the fifo size

	 * - Half the period size

	 */

	threshold = min(period / 2,

			(unsigned int)AXG_FIFO_MIN_DEPTH / 2);

	threshold = min(period / 2, fifo->depth / 2);



	/*

	 * With the threshold in bytes, register value is:
@@ -320,6 +319,7 @@ int axg_fifo_probe(struct platform_device *pdev) 
	const struct axg_fifo_match_data *data;

	struct axg_fifo *fifo;

	void __iomem *regs;

	int ret;



	data = of_device_get_match_data(dev);

	if (!data) {
@@ -370,6 +370,21 @@ int axg_fifo_probe(struct platform_device *pdev) 
	if (IS_ERR(fifo->field_threshold))

		return PTR_ERR(fifo->field_threshold);



	ret = of_property_read_u32(dev->of_node, "amlogic,fifo-depth",

				   &fifo->depth);

	if (ret) {

		/* Error out for anything but a missing property */

		if (ret != -EINVAL)

			return ret;

		/*

		 * If the property is missing, it might be because of an old

		 * DT. In such case, assume the smallest known fifo depth

		 */

		fifo->depth = 256;

		dev_warn(dev, "fifo depth not found, assume %u bytes\n",

			 fifo->depth);

	}



	return devm_snd_soc_register_component(dev, data->component_drv,

					       data->dai_drv, 1);

}

sound/soc/meson/axg-fifo.h

+1 −0
Original line number Diff line number Diff line
@@ -68,6 +68,7 @@ struct axg_fifo { 
	struct clk *pclk;

	struct reset_control *arb;

	struct regmap_field *field_threshold;

	unsigned int depth;

	int irq;

};

sound/soc/meson/axg-frddr.c

+4 −9
Original line number Diff line number Diff line
@@ -50,7 +50,7 @@ static int axg_frddr_dai_startup(struct snd_pcm_substream *substream, 
				 struct snd_soc_dai *dai)

{

	struct axg_fifo *fifo = snd_soc_dai_get_drvdata(dai);

	unsigned int fifo_depth;

	unsigned int val;

	int ret;



	/* Enable pclk to access registers and clock the fifo ip */
@@ -61,15 +61,10 @@ static int axg_frddr_dai_startup(struct snd_pcm_substream *substream, 
	/* Apply single buffer mode to the interface */

	regmap_update_bits(fifo->map, FIFO_CTRL0, CTRL0_FRDDR_PP_MODE, 0);



	/*

	 * TODO: We could adapt the fifo depth and the fifo threshold

	 * depending on the expected memory throughput and lantencies

	 * For now, we'll just use the same values as the vendor kernel

	 * Depth and threshold are zero based.

	 */

	fifo_depth = AXG_FIFO_MIN_CNT - 1;

	/* Use all fifo depth */

	val = (fifo->depth / AXG_FIFO_BURST) - 1;

	regmap_update_bits(fifo->map, FIFO_CTRL1, CTRL1_FRDDR_DEPTH_MASK,

			   CTRL1_FRDDR_DEPTH(fifo_depth));

			   CTRL1_FRDDR_DEPTH(val));



	return 0;

}

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