Commit 23956dfa authored by Dave Airlie's avatar Dave Airlie
Browse files

drm/radeon/kms: add HDP flushing for all GPUs. 



rendercheck under kms on r600s was failing due to HDP flushing not happening.

This adds HDP flushing to the object wait function for r100->r700 families.

rendercheck passes basic tests on r600 with this change.

Acked-by: default avatarAlex Deucher <alexdeucher@gmail.com>
Signed-off-by: default avatarDave Airlie <airlied@redhat.com>
parent 38e14921

drivers/gpu/drm/radeon/r100.c

+8 −0
Original line number Diff line number Diff line
@@ -1589,6 +1589,14 @@ void r100_gpu_init(struct radeon_device *rdev) 
	r100_hdp_reset(rdev);

}



void r100_hdp_flush(struct radeon_device *rdev)

{

	u32 tmp;

	tmp = RREG32(RADEON_HOST_PATH_CNTL);

	tmp |= RADEON_HDP_READ_BUFFER_INVALIDATE;

	WREG32(RADEON_HOST_PATH_CNTL, tmp);

}



void r100_hdp_reset(struct radeon_device *rdev)

{

	uint32_t tmp;

drivers/gpu/drm/radeon/r600.c

+4 −0
Original line number Diff line number Diff line
@@ -1101,6 +1101,10 @@ void r600_pciep_wreg(struct radeon_device *rdev, u32 reg, u32 v) 
	(void)RREG32(PCIE_PORT_DATA);

}



void r600_hdp_flush(struct radeon_device *rdev)

{

	WREG32(R_005480_HDP_MEM_COHERENCY_FLUSH_CNTL, 0x1);

}



/*

 * CP & Ring

drivers/gpu/drm/radeon/r600d.h

+1 −0
Original line number Diff line number Diff line
@@ -674,4 +674,5 @@ 
#define		S_000E60_SOFT_RESET_TSC(x)		(((x) & 1) << 16)

#define		S_000E60_SOFT_RESET_VMC(x)		(((x) & 1) << 17)



#define R_005480_HDP_MEM_COHERENCY_FLUSH_CNTL		0x5480

#endif

drivers/gpu/drm/radeon/radeon.h

+2 −0
Original line number Diff line number Diff line
@@ -639,6 +639,7 @@ struct radeon_asic { 
			       uint32_t offset, uint32_t obj_size);

	int (*clear_surface_reg)(struct radeon_device *rdev, int reg);

	void (*bandwidth_update)(struct radeon_device *rdev);

	void (*hdp_flush)(struct radeon_device *rdev);

};



/*
@@ -971,6 +972,7 @@ static inline void radeon_ring_write(struct radeon_device *rdev, uint32_t v) 
#define radeon_set_surface_reg(rdev, r, f, p, o, s) ((rdev)->asic->set_surface_reg((rdev), (r), (f), (p), (o), (s)))

#define radeon_clear_surface_reg(rdev, r) ((rdev)->asic->clear_surface_reg((rdev), (r)))

#define radeon_bandwidth_update(rdev) (rdev)->asic->bandwidth_update((rdev))

#define radeon_hdp_flush(rdev) (rdev)->asic->hdp_flush((rdev))



/* Common functions */

extern int radeon_gart_table_vram_pin(struct radeon_device *rdev);

drivers/gpu/drm/radeon/radeon_asic.h

+12 −0
Original line number Diff line number Diff line
@@ -76,6 +76,7 @@ int r100_clear_surface_reg(struct radeon_device *rdev, int reg); 
void r100_bandwidth_update(struct radeon_device *rdev);

void r100_ring_ib_execute(struct radeon_device *rdev, struct radeon_ib *ib);

int r100_ring_test(struct radeon_device *rdev);

void r100_hdp_flush(struct radeon_device *rdev);



static struct radeon_asic r100_asic = {

	.init = &r100_init,
@@ -107,6 +108,7 @@ static struct radeon_asic r100_asic = { 
	.set_surface_reg = r100_set_surface_reg,

	.clear_surface_reg = r100_clear_surface_reg,

	.bandwidth_update = &r100_bandwidth_update,

	.hdp_flush = &r100_hdp_flush,

};
@@ -162,6 +164,7 @@ static struct radeon_asic r300_asic = { 
	.set_surface_reg = r100_set_surface_reg,

	.clear_surface_reg = r100_clear_surface_reg,

	.bandwidth_update = &r100_bandwidth_update,

	.hdp_flush = &r100_hdp_flush,

};



/*
@@ -201,6 +204,7 @@ static struct radeon_asic r420_asic = { 
	.set_surface_reg = r100_set_surface_reg,

	.clear_surface_reg = r100_clear_surface_reg,

	.bandwidth_update = &r100_bandwidth_update,

	.hdp_flush = &r100_hdp_flush,

};
@@ -245,6 +249,7 @@ static struct radeon_asic rs400_asic = { 
	.set_surface_reg = r100_set_surface_reg,

	.clear_surface_reg = r100_clear_surface_reg,

	.bandwidth_update = &r100_bandwidth_update,

	.hdp_flush = &r100_hdp_flush,

};
@@ -291,6 +296,7 @@ static struct radeon_asic rs600_asic = { 
	.set_pcie_lanes = NULL,

	.set_clock_gating = &radeon_atom_set_clock_gating,

	.bandwidth_update = &rs600_bandwidth_update,

	.hdp_flush = &r100_hdp_flush,

};
@@ -334,6 +340,7 @@ static struct radeon_asic rs690_asic = { 
	.set_surface_reg = r100_set_surface_reg,

	.clear_surface_reg = r100_clear_surface_reg,

	.bandwidth_update = &rs690_bandwidth_update,

	.hdp_flush = &r100_hdp_flush,

};
@@ -381,6 +388,7 @@ static struct radeon_asic rv515_asic = { 
	.set_surface_reg = r100_set_surface_reg,

	.clear_surface_reg = r100_clear_surface_reg,

	.bandwidth_update = &rv515_bandwidth_update,

	.hdp_flush = &r100_hdp_flush,

};
@@ -419,6 +427,7 @@ static struct radeon_asic r520_asic = { 
	.set_surface_reg = r100_set_surface_reg,

	.clear_surface_reg = r100_clear_surface_reg,

	.bandwidth_update = &rv515_bandwidth_update,

	.hdp_flush = &r100_hdp_flush,

};



/*
@@ -455,6 +464,7 @@ int r600_ring_test(struct radeon_device *rdev); 
int r600_copy_blit(struct radeon_device *rdev,

		   uint64_t src_offset, uint64_t dst_offset,

		   unsigned num_pages, struct radeon_fence *fence);

void r600_hdp_flush(struct radeon_device *rdev);



static struct radeon_asic r600_asic = {

	.init = &r600_init,
@@ -484,6 +494,7 @@ static struct radeon_asic r600_asic = { 
	.set_surface_reg = r600_set_surface_reg,

	.clear_surface_reg = r600_clear_surface_reg,

	.bandwidth_update = &rv515_bandwidth_update,

	.hdp_flush = &r600_hdp_flush,

};



/*
@@ -523,6 +534,7 @@ static struct radeon_asic rv770_asic = { 
	.set_surface_reg = r600_set_surface_reg,

	.clear_surface_reg = r600_clear_surface_reg,

	.bandwidth_update = &rv515_bandwidth_update,

	.hdp_flush = &r600_hdp_flush,

};



#endif

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