Merge branch 'berlin/soc' into next/soc

   Linux kernel mach directory: arch/arm/mach-mmp

   Linux kernel plat directory: arch/arm/plat-pxa

Berlin family (Digital Entertainment)

-------------------------------------

  Flavors:

	88DE3005, Armada 1500-mini

		Design name:	BG2CD

		Core:		ARM Cortex-A9, PL310 L2CC

		Homepage:	http://www.marvell.com/digital-entertainment/armada-1500-mini/

	88DE3100, Armada 1500

		Design name:	BG2

		Core:		Marvell PJ4B (ARMv7), Tauros3 L2CC

		Homepage:	http://www.marvell.com/digital-entertainment/armada-1500/

		Product Brief:	http://www.marvell.com/digital-entertainment/armada-1500/assets/Marvell-ARMADA-1500-Product-Brief.pdf

	88DE????

		Design name:	BG3

		Core:		ARM Cortex-A15, CA15 integrated L2CC

  Homepage: http://www.marvell.com/digital-entertainment/

  Directory: arch/arm/mach-berlin

  Comments:

   * This line of SoCs is based on Marvell Sheeva or ARM Cortex CPUs

     with Synopsys DesignWare (IRQ, GPIO, Timers, ...) and PXA IP (SDHCI, USB, ETH, ...).

Long-term plans

---------------

Marvell Berlin SoC Family Device Tree Bindings

---------------------------------------------------------------

Boards with a SoC of the Marvell Berlin family, e.g. Armada 1500

shall have the following properties:

* Required root node properties:

compatible: must contain "marvell,berlin"

In addition, the above compatible shall be extended with the specific

SoC and board used. Currently known SoC compatibles are:

    "marvell,berlin2"      for Marvell Armada 1500 (BG2, 88DE3100),

    "marvell,berlin2cd"    for Marvell Armada 1500-mini (BG2CD, 88DE3005)

    "marvell,berlin2ct"    for Marvell Armada ? (BG2CT, 88DE????)

    "marvell,berlin3"      for Marvell Armada ? (BG3, 88DE????)

* Example:

/ {

	model = "Sony NSZ-GS7";

	compatible = "sony,nsz-gs7", "marvell,berlin2", "marvell,berlin";

	...

}

Synopsys DesignWare APB interrupt controller (dw_apb_ictl)

Synopsys DesignWare provides interrupt controller IP for APB known as

dw_apb_ictl. The IP is used as secondary interrupt controller in some SoCs with

APB bus, e.g. Marvell Armada 1500.

Required properties:

- compatible: shall be "snps,dw-apb-ictl"

- reg: physical base address of the controller and length of memory mapped

  region starting with ENABLE_LOW register

- interrupt-controller: identifies the node as an interrupt controller

- #interrupt-cells: number of cells to encode an interrupt-specifier, shall be 1

- interrupts: interrupt reference to primary interrupt controller

- interrupt-parent: (optional) reference specific primary interrupt controller

The interrupt sources map to the corresponding bits in the interrupt

registers, i.e.

- 0 maps to bit 0 of low interrupts,

- 1 maps to bit 1 of low interrupts,

- 32 maps to bit 0 of high interrupts,

- 33 maps to bit 1 of high interrupts,

- (optional) fast interrupts start at 64.

Example:

	aic: interrupt-controller@3000 {

		compatible = "snps,dw-apb-ictl";

		reg = <0x3000 0xc00>;

		interrupt-controller;

		#interrupt-cells = <1>;

		interrupt-parent = <&gic>;

		interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>;

	};

S:	Maintained

F:	arch/arm/mach-mvebu/

ARM/Marvell Berlin SoC support

M:	Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>

L:	linux-arm-kernel@lists.infradead.org (moderated for non-subscribers)

S:	Maintained

F:	arch/arm/mach-berlin/

ARM/Marvell Dove/Kirkwood/MV78xx0/Orion SOC support

M:	Jason Cooper <jason@lakedaemon.net>

M:	Andrew Lunn <andrew@lunn.ch>

source "arch/arm/mach-bcm2835/Kconfig"

source "arch/arm/mach-berlin/Kconfig"

source "arch/arm/mach-clps711x/Kconfig"

source "arch/arm/mach-cns3xxx/Kconfig"