Commit 23588c38 authored by Andreas Herrmann's avatar Andreas Herrmann Committed by H. Peter Anvin
Browse files

x86, amd: Add support for CPUID topology extension of AMD CPUs 



Node information (ID, number of internal nodes) is provided via
CPUID Fn8000_001e_ECX.

See AMD CPUID Specification (Publication # 25481, Revision 2.34,
September 2010).

Signed-off-by: default avatarAndreas Herrmann <andreas.herrmann3@amd.com>
LKML-Reference: <20100930123628.GD20545@loge.amd.com>
Signed-off-by: default avatarH. Peter Anvin <hpa@linux.intel.com>
parent 420b13b6

arch/x86/kernel/cpu/amd.c

+26 −24
Original line number Original line Diff line number Diff line
@@ -253,38 +253,42 @@ static int __cpuinit nearby_node(int apicid) 
#endif

#endif





/*

/*

 * Fixup core topology information for AMD multi-node processors.

 * Fixup core topology information for

 * (1) AMD multi-node processors

 *     Assumption: Number of cores in each internal node is the same.

 *     Assumption: Number of cores in each internal node is the same.

 */

 */

#ifdef CONFIG_X86_HT

#ifdef CONFIG_X86_HT

static void __cpuinit amd_fixup_dcm(struct cpuinfo_x86 *c)

static void __cpuinit amd_get_topology(struct cpuinfo_x86 *c)

{

{

	unsigned long long value;

	u32 nodes, cores_per_node;

	u32 nodes, cores_per_node;

	u8 node_id;

	unsigned long long value;

	int cpu = smp_processor_id();

	int cpu = smp_processor_id();





	if (!cpu_has(c, X86_FEATURE_NODEID_MSR))

	/* get information required for multi-node processors */

		return;

	if (cpu_has(c, X86_FEATURE_TOPOEXT)) {



		value = cpuid_ecx(0x8000001e);

	/* fixup topology information only once for a core */

		nodes = ((value >> 8) & 7) + 1;

	if (cpu_has(c, X86_FEATURE_AMD_DCM))

		node_id = value & 7;

		return;

	} else if (cpu_has(c, X86_FEATURE_NODEID_MSR)) {



		rdmsrl(MSR_FAM10H_NODE_ID, value);

		rdmsrl(MSR_FAM10H_NODE_ID, value);



		nodes = ((value >> 3) & 7) + 1;

		nodes = ((value >> 3) & 7) + 1;

	if (nodes == 1)

		node_id = value & 7;

	} else

		return;

		return;





	/* fixup multi-node processor information */

	if (nodes > 1) {

		set_cpu_cap(c, X86_FEATURE_AMD_DCM);

		set_cpu_cap(c, X86_FEATURE_AMD_DCM);

		cores_per_node = c->x86_max_cores / nodes;

		cores_per_node = c->x86_max_cores / nodes;





		/* store NodeID, use llc_shared_map to store sibling info */

		/* store NodeID, use llc_shared_map to store sibling info */

	per_cpu(cpu_llc_id, cpu) = value & 7;

		per_cpu(cpu_llc_id, cpu) = node_id;





	/* fixup core id to be in range from 0 to (cores_per_node - 1) */

		/* core id to be in range from 0 to (cores_per_node - 1) */

		c->cpu_core_id = c->cpu_core_id % cores_per_node;

		c->cpu_core_id = c->cpu_core_id % cores_per_node;

	}

	}

}

#endif

#endif





/*

/*
@@ -304,9 +308,7 @@ static void __cpuinit amd_detect_cmp(struct cpuinfo_x86 *c) 
	c->phys_proc_id = c->initial_apicid >> bits;

	c->phys_proc_id = c->initial_apicid >> bits;

	/* use socket ID also for last level cache */

	/* use socket ID also for last level cache */

	per_cpu(cpu_llc_id, cpu) = c->phys_proc_id;

	per_cpu(cpu_llc_id, cpu) = c->phys_proc_id;

	/* fixup topology information on multi-node processors */

	amd_get_topology(c);

	if ((c->x86 == 0x10) && (c->x86_model == 9))

		amd_fixup_dcm(c);

#endif

#endif

}

}

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