Commit 234b6ced authored by Russell King's avatar Russell King
Browse files

clocksource: convert ARM 32-bit up counting clocksources 



Convert ixp4xx, lpc32xx, mxc, netx, pxa, sa1100, tcc8k, tegra and u300
to use the generic mmio clocksource recently introduced.

Cc: Imre Kaloz <kaloz@openwrt.org>
Cc: Krzysztof Halasa <khc@pm.waw.pl>
Acked-by: default avatarEric Miao <eric.y.miao@gmail.com>
Acked-by: default avatar"Hans J. Koch" <hjk@hansjkoch.de>
Acked-by: default avatarColin Cross <ccross@android.com>
Cc: Erik Gilling <konkers@android.com>
Cc: Olof Johansson <olof@lixom.net>
Acked-by: default avatarLinus Walleij <linus.walleij@linaro.org>
Acked-by: default avatarSascha Hauer <s.hauer@pengutronix.de>
Signed-off-by: default avatarRussell King <rmk+kernel@arm.linux.org.uk>
parent 442c8176

arch/arm/Kconfig

+9 −0
Original line number Diff line number Diff line
@@ -366,6 +366,7 @@ config ARCH_MXC 
	select GENERIC_CLOCKEVENTS

	select ARCH_REQUIRE_GPIOLIB

	select CLKDEV_LOOKUP

	select CLKSRC_MMIO

	select HAVE_SCHED_CLOCK

	help

	  Support for Freescale MXC/iMX-based family of processors
@@ -390,6 +391,7 @@ config ARCH_STMP3XXX 


config ARCH_NETX

	bool "Hilscher NetX based"

	select CLKSRC_MMIO

	select CPU_ARM926T

	select ARM_VIC

	select GENERIC_CLOCKEVENTS
@@ -457,6 +459,7 @@ config ARCH_IXP2000 
config ARCH_IXP4XX

	bool "IXP4xx-based"

	depends on MMU

	select CLKSRC_MMIO

	select CPU_XSCALE

	select GENERIC_GPIO

	select GENERIC_CLOCKEVENTS
@@ -497,6 +500,7 @@ config ARCH_LOKI 


config ARCH_LPC32XX

	bool "NXP LPC32XX"

	select CLKSRC_MMIO

	select CPU_ARM926T

	select ARCH_REQUIRE_GPIOLIB

	select HAVE_IDE
@@ -592,6 +596,7 @@ config ARCH_NUC93X 
config ARCH_TEGRA

	bool "NVIDIA Tegra"

	select CLKDEV_LOOKUP

	select CLKSRC_MMIO

	select GENERIC_TIME

	select GENERIC_CLOCKEVENTS

	select GENERIC_GPIO
@@ -617,6 +622,7 @@ config ARCH_PXA 
	select ARCH_MTD_XIP

	select ARCH_HAS_CPUFREQ

	select CLKDEV_LOOKUP

	select CLKSRC_MMIO

	select ARCH_REQUIRE_GPIOLIB

	select GENERIC_CLOCKEVENTS

	select HAVE_SCHED_CLOCK
@@ -667,6 +673,7 @@ config ARCH_RPC 


config ARCH_SA1100

	bool "SA1100-based"

	select CLKSRC_MMIO

	select CPU_SA1100

	select ISA

	select ARCH_SPARSEMEM_ENABLE
@@ -803,6 +810,7 @@ config ARCH_SHARK 


config ARCH_TCC_926

	bool "Telechips TCC ARM926-based systems"

	select CLKSRC_MMIO

	select CPU_ARM926T

	select HAVE_CLK

	select CLKDEV_LOOKUP
@@ -813,6 +821,7 @@ config ARCH_TCC_926 
config ARCH_U300

	bool "ST-Ericsson U300 Series"

	depends on MMU

	select CLKSRC_MMIO

	select CPU_ARM926T

	select HAVE_SCHED_CLOCK

	select HAVE_TCM

arch/arm/mach-ixp4xx/common.c

+2 −14
Original line number Diff line number Diff line
@@ -419,26 +419,14 @@ static void notrace ixp4xx_update_sched_clock(void) 
/*

 * clocksource

 */

static cycle_t ixp4xx_get_cycles(struct clocksource *cs)

{

	return *IXP4XX_OSTS;

}



static struct clocksource clocksource_ixp4xx = {

	.name 		= "OSTS",

	.rating		= 200,

	.read		= ixp4xx_get_cycles,

	.mask		= CLOCKSOURCE_MASK(32),

	.flags		= CLOCK_SOURCE_IS_CONTINUOUS,

};



unsigned long ixp4xx_timer_freq = IXP4XX_TIMER_FREQ;

EXPORT_SYMBOL(ixp4xx_timer_freq);

static void __init ixp4xx_clocksource_init(void)

{

	init_sched_clock(&cd, ixp4xx_update_sched_clock, 32, ixp4xx_timer_freq);



	clocksource_register_hz(&clocksource_ixp4xx, ixp4xx_timer_freq);

	clocksource_mmio_init(&IXP4XX_OSTS, "OSTS", ixp4xx_timer_freq, 200, 32,

			clocksource_mmio_readl_up);

}



/*

arch/arm/mach-lpc32xx/timer.c

+3 −14
Original line number Diff line number Diff line
@@ -31,19 +31,6 @@ 
#include <mach/platform.h>

#include "common.h"



static cycle_t lpc32xx_clksrc_read(struct clocksource *cs)

{

	return (cycle_t)__raw_readl(LCP32XX_TIMER_TC(LPC32XX_TIMER1_BASE));

}



static struct clocksource lpc32xx_clksrc = {

	.name	= "lpc32xx_clksrc",

	.rating	= 300,

	.read	= lpc32xx_clksrc_read,

	.mask	= CLOCKSOURCE_MASK(32),

	.flags	= CLOCK_SOURCE_IS_CONTINUOUS,

};



static int lpc32xx_clkevt_next_event(unsigned long delta,

    struct clock_event_device *dev)

{
@@ -170,7 +157,9 @@ static void __init lpc32xx_timer_init(void) 
	__raw_writel(0, LCP32XX_TIMER_MCR(LPC32XX_TIMER1_BASE));

	__raw_writel(LCP32XX_TIMER_CNTR_TCR_EN,

		LCP32XX_TIMER_TCR(LPC32XX_TIMER1_BASE));

	clocksource_register_hz(&lpc32xx_clksrc, clkrate);



	clocksource_mmio_init(LCP32XX_TIMER_TC(LPC32XX_TIMER1_BASE),

		"lpc32xx_clksrc", clkrate, 300, 32, clocksource_mmio_readl_up);

}



struct sys_timer lpc32xx_timer = {

arch/arm/mach-netx/time.c

+2 −14
Original line number Diff line number Diff line
@@ -104,19 +104,6 @@ static struct irqaction netx_timer_irq = { 
	.handler	= netx_timer_interrupt,

};



cycle_t netx_get_cycles(struct clocksource *cs)

{

	return readl(NETX_GPIO_COUNTER_CURRENT(TIMER_CLOCKSOURCE));

}



static struct clocksource clocksource_netx = {

	.name		= "netx_timer",

	.rating		= 200,

	.read		= netx_get_cycles,

	.mask		= CLOCKSOURCE_MASK(32),

	.flags		= CLOCK_SOURCE_IS_CONTINUOUS,

};



/*

 * Set up timer interrupt

 */
@@ -150,7 +137,8 @@ static void __init netx_timer_init(void) 
	writel(NETX_GPIO_COUNTER_CTRL_RUN,

			NETX_GPIO_COUNTER_CTRL(TIMER_CLOCKSOURCE));



	clocksource_register_hz(&clocksource_netx, CLOCK_TICK_RATE);

	clocksource_mmio_init(NETX_GPIO_COUNTER_CURRENT(TIMER_CLOCKSOURCE),

		"netx_timer", CLOCK_TICK_RATE, 200, 32, clocksource_mmio_readl_up);



	netx_clockevent.mult = div_sc(CLOCK_TICK_RATE, NSEC_PER_SEC,

			netx_clockevent.shift);

arch/arm/mach-pxa/time.c

+2 −15
Original line number Diff line number Diff line
@@ -105,19 +105,6 @@ static struct clock_event_device ckevt_pxa_osmr0 = { 
	.set_mode	= pxa_osmr0_set_mode,

};



static cycle_t pxa_read_oscr(struct clocksource *cs)

{

	return OSCR;

}



static struct clocksource cksrc_pxa_oscr0 = {

	.name           = "oscr0",

	.rating         = 200,

	.read           = pxa_read_oscr,

	.mask           = CLOCKSOURCE_MASK(32),

	.flags		= CLOCK_SOURCE_IS_CONTINUOUS,

};



static struct irqaction pxa_ost0_irq = {

	.name		= "ost0",

	.flags		= IRQF_DISABLED | IRQF_TIMER | IRQF_IRQPOLL,
@@ -134,7 +121,6 @@ static void __init pxa_timer_init(void) 


	init_sched_clock(&cd, pxa_update_sched_clock, 32, clock_tick_rate);



	clocksource_calc_mult_shift(&cksrc_pxa_oscr0, clock_tick_rate, 4);

	clockevents_calc_mult_shift(&ckevt_pxa_osmr0, clock_tick_rate, 4);

	ckevt_pxa_osmr0.max_delta_ns =

		clockevent_delta2ns(0x7fffffff, &ckevt_pxa_osmr0);
@@ -144,7 +130,8 @@ static void __init pxa_timer_init(void) 


	setup_irq(IRQ_OST0, &pxa_ost0_irq);



	clocksource_register_hz(&cksrc_pxa_oscr0, clock_tick_rate);

	clocksource_mmio_init(&OSCR, "oscr0", clock_tick_rate, 200, 32,

		clocksource_mmio_readl_up);

	clockevents_register_device(&ckevt_pxa_osmr0);

}

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