Commit 23308c54 authored by Michael Barkowski's avatar Michael Barkowski Committed by Kumar Gala
Browse files

[POWERPC] 83xx: Add MPC832x RDB board support. 



Add support for the MPC8323E Reference Development Board (RDB).  The board
is a mini-ITX reference board with 64M DDR2, 16M flash, USB, PCI,
10/100 ethernet, serial, and phone ports.

Signed-off-by: default avatarMichael Barkowski <michael.barkowski@freescale.com>
Signed-off-by: default avatarKim Phillips <kim.phillips@freescale.com>
Signed-off-by: default avatarKumar Gala <galak@kernel.crashing.org>
parent 1a4d9399

arch/powerpc/boot/dts/mpc832x_rdb.dts

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/*

 * MPC832x RDB Device Tree Source

 *

 * Copyright 2007 Freescale Semiconductor Inc.

 *

 * This program is free software; you can redistribute  it and/or modify it

 * under  the terms of  the GNU General  Public License as published by the

 * Free Software Foundation;  either version 2 of the  License, or (at your

 * option) any later version.

 */



/ {

	model = "MPC8323ERDB";

	compatible = "MPC8323ERDB", "MPC832xRDB", "MPC83xxRDB";

	#address-cells = <1>;

	#size-cells = <1>;



	cpus {

		#address-cells = <1>;

		#size-cells = <0>;



		PowerPC,8323@0 {

			device_type = "cpu";

			reg = <0>;

			d-cache-line-size = <20>;	// 32 bytes

			i-cache-line-size = <20>;	// 32 bytes

			d-cache-size = <4000>;		// L1, 16K

			i-cache-size = <4000>;		// L1, 16K

			timebase-frequency = <0>;

			bus-frequency = <0>;

			clock-frequency = <0>;

			32-bit;

		};

	};



	memory {

		device_type = "memory";

		reg = <00000000 04000000>;

	};



	soc8323@e0000000 {

		#address-cells = <1>;

		#size-cells = <1>;

		#interrupt-cells = <2>;

		device_type = "soc";

		ranges = <0 e0000000 00100000>;

		reg = <e0000000 00000200>;

		bus-frequency = <0>;



		wdt@200 {

			device_type = "watchdog";

			compatible = "mpc83xx_wdt";

			reg = <200 100>;

		};



		i2c@3000 {

			device_type = "i2c";

			compatible = "fsl-i2c";

			reg = <3000 100>;

			interrupts = <e 8>;

			interrupt-parent = <&pic>;

			dfsrr;

		};



		serial@4500 {

			device_type = "serial";

			compatible = "ns16550";

			reg = <4500 100>;

			clock-frequency = <0>;

			interrupts = <9 8>;

			interrupt-parent = <&pic>;

		};



		serial@4600 {

			device_type = "serial";

			compatible = "ns16550";

			reg = <4600 100>;

			clock-frequency = <0>;

			interrupts = <a 8>;

			interrupt-parent = <&pic>;

		};



		crypto@30000 {

			device_type = "crypto";

			model = "SEC2";

			compatible = "talitos";

			reg = <30000 7000>;

			interrupts = <b 8>;

			interrupt-parent = <&pic>;

			/* Rev. 2.2 */

			num-channels = <1>;

			channel-fifo-len = <18>;

			exec-units-mask = <0000004c>;

			descriptor-types-mask = <0122003f>;

		};



		pci@8500 {

			interrupt-map-mask = <f800 0 0 7>;

			interrupt-map = <

					/* IDSEL 0x10 AD16 (USB) */

					 8000 0 0 1 &pic 11 8



					/* IDSEL 0x11 AD17 (Mini1)*/

					 8800 0 0 1 &pic 12 8

					 8800 0 0 2 &pic 13 8

					 8800 0 0 3 &pic 14 8

					 8800 0 0 4 &pic 30 8



					/* IDSEL 0x12 AD18 (PCI/Mini2) */

					 9000 0 0 1 &pic 13 8

					 9000 0 0 2 &pic 14 8

					 9000 0 0 3 &pic 30 8

					 9000 0 0 4 &pic 11 8>;



			interrupt-parent = <&pic>;

			interrupts = <42 8>;

			bus-range = <0 0>;

			ranges = <42000000 0 80000000 80000000 0 10000000

			          02000000 0 90000000 90000000 0 10000000

			          01000000 0 d0000000 d0000000 0 04000000>;

			clock-frequency = <0>;

			#interrupt-cells = <1>;

			#size-cells = <2>;

			#address-cells = <3>;

			reg = <8500 100>;

			compatible = "83xx";

			device_type = "pci";

		};



		pic:pic@700 {

			interrupt-controller;

			#address-cells = <0>;

			#interrupt-cells = <2>;

			reg = <700 100>;

			built-in;

			device_type = "ipic";

		};



		par_io@1400 {

			reg = <1400 100>;

			device_type = "par_io";

			num-ports = <7>;



			ucc2pio:ucc_pin@02 {

				pio-map = <

			/* port  pin  dir  open_drain  assignment  has_irq */

					3  4  3  0  2  0 	/* MDIO */

					3  5  1  0  2  0 	/* MDC */

					3 15  2  0  1  0 	/* RX_CLK (CLK16) */

					3 17  2  0  1  0 	/* TX_CLK (CLK3) */

					0 12  1  0  1  0 	/* TxD0 */

					0 13  1  0  1  0 	/* TxD1 */

					0 14  1  0  1  0 	/* TxD2 */

					0 15  1  0  1  0 	/* TxD3 */

					0 16  2  0  1  0 	/* RxD0 */

					0 17  2  0  1  0 	/* RxD1 */

					0 18  2  0  1  0 	/* RxD2 */

					0 19  2  0  1  0 	/* RxD3 */

					0 1a  2  0  1  0 	/* RX_ER */

					0 1b  1  0  1  0 	/* TX_ER */

					0 1c  2  0  1  0 	/* RX_DV */

					0 1d  2  0  1  0 	/* COL */

					0 1e  1  0  1  0 	/* TX_EN */

					0 1f  2  0  1  0>;      /* CRS */

			};

			ucc3pio:ucc_pin@03 {

				pio-map = <

			/* port  pin  dir  open_drain  assignment  has_irq */

					0  d  2  0  1  0 	/* RX_CLK (CLK9) */

					3 18  2  0  1  0 	/* TX_CLK (CLK10) */

					1  0  1  0  1  0 	/* TxD0 */

					1  1  1  0  1  0 	/* TxD1 */

					1  2  1  0  1  0 	/* TxD2 */

					1  3  1  0  1  0 	/* TxD3 */

					1  4  2  0  1  0 	/* RxD0 */

					1  5  2  0  1  0 	/* RxD1 */

					1  6  2  0  1  0 	/* RxD2 */

					1  7  2  0  1  0 	/* RxD3 */

					1  8  2  0  1  0 	/* RX_ER */

					1  9  1  0  1  0 	/* TX_ER */

					1  a  2  0  1  0 	/* RX_DV */

					1  b  2  0  1  0 	/* COL */

					1  c  1  0  1  0 	/* TX_EN */

					1  d  2  0  1  0>;      /* CRS */

			};

		};

	};



	qe@e0100000 {

		#address-cells = <1>;

		#size-cells = <1>;

		device_type = "qe";

		model = "QE";

		ranges = <0 e0100000 00100000>;

		reg = <e0100000 480>;

		brg-frequency = <0>;

		bus-frequency = <BCD3D80>;



		muram@10000 {

			device_type = "muram";

			ranges = <0 00010000 00004000>;



			data-only@0 {

				reg = <0 4000>;

			};

		};



		spi@4c0 {

			device_type = "spi";

			compatible = "fsl_spi";

			reg = <4c0 40>;

			interrupts = <2>;

			interrupt-parent = <&qeic>;

			mode = "cpu";

		};



		spi@500 {

			device_type = "spi";

			compatible = "fsl_spi";

			reg = <500 40>;

			interrupts = <1>;

			interrupt-parent = <&qeic>;

			mode = "cpu";

		};



		ucc@3000 {

			device_type = "network";

			compatible = "ucc_geth";

			model = "UCC";

			device-id = <2>;

			reg = <3000 200>;

			interrupts = <21>;

			interrupt-parent = <&qeic>;

			mac-address = [ 00 04 9f ef 03 02 ];

			rx-clock = <20>;

			tx-clock = <13>;

			phy-handle = <&phy00>;

			pio-handle = <&ucc2pio>;

		};



		ucc@2200 {

			device_type = "network";

			compatible = "ucc_geth";

			model = "UCC";

			device-id = <3>;

			reg = <2200 200>;

			interrupts = <22>;

			interrupt-parent = <&qeic>;

			mac-address = [ 00 04 9f ef 03 01 ];

			rx-clock = <19>;

			tx-clock = <1a>;

			phy-handle = <&phy04>;

			pio-handle = <&ucc3pio>;

		};



		mdio@3120 {

			#address-cells = <1>;

			#size-cells = <0>;

			reg = <3120 18>;

			device_type = "mdio";

			compatible = "ucc_geth_phy";



			phy00:ethernet-phy@00 {

				interrupt-parent = <&pic>;

				interrupts = <0>;

				reg = <0>;

				device_type = "ethernet-phy";

				interface = <3>; //ENET_100_MII

			};

			phy04:ethernet-phy@04 {

				interrupt-parent = <&pic>;

				interrupts = <0>;

				reg = <4>;

				device_type = "ethernet-phy";

				interface = <3>;

			};

		};



		qeic:qeic@80 {

			interrupt-controller;

			device_type = "qeic";

			#address-cells = <0>;

			#interrupt-cells = <1>;

			reg = <80 80>;

			built-in;

			big-endian;

			interrupts = <20 8 21 8>; //high:32 low:33

			interrupt-parent = <&pic>;

		};

	};

};

arch/powerpc/configs/mpc832x_rdb_defconfig

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File added.

Preview size limit exceeded, changes collapsed.

arch/powerpc/platforms/83xx/Kconfig

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@@ -18,6 +18,13 @@ config MPC832x_MDS 
	help

	  This option enables support for the MPC832x MDS evaluation board.



config MPC832x_RDB

	bool "Freescale MPC832x RDB"

	select DEFAULT_UIMAGE

	select QUICC_ENGINE

	help

	  This option enables support for the MPC8323 RDB board.



config MPC834x_MDS

	bool "Freescale MPC834x MDS"

	select DEFAULT_UIMAGE
@@ -57,7 +64,7 @@ config PPC_MPC832x 
	bool

	select PPC_UDBG_16550

	select PPC_INDIRECT_PCI

	default y if MPC832x_MDS

	default y if MPC832x_MDS || MPC832x_RDB



config MPC834x

	bool

arch/powerpc/platforms/83xx/Makefile

+1 −0
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@@ -4,6 +4,7 @@ 
obj-y				:= misc.o

obj-$(CONFIG_PCI)		+= pci.o

obj-$(CONFIG_MPC8313_RDB)	+= mpc8313_rdb.o

obj-$(CONFIG_MPC832x_RDB)	+= mpc832x_rdb.o

obj-$(CONFIG_MPC834x_MDS)	+= mpc834x_mds.o

obj-$(CONFIG_MPC834x_ITX)	+= mpc834x_itx.o

obj-$(CONFIG_MPC836x_MDS)	+= mpc836x_mds.o

arch/powerpc/platforms/83xx/mpc832x_rdb.c

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/*

 * arch/powerpc/platforms/83xx/mpc832x_rdb.c

 *

 * Copyright (C) Freescale Semiconductor, Inc. 2007. All rights reserved.

 *

 * Description:

 * MPC832x RDB board specific routines.

 * This file is based on mpc832x_mds.c and mpc8313_rdb.c

 * Author: Michael Barkowski <michael.barkowski@freescale.com>

 *

 * This program is free software; you can redistribute  it and/or modify it

 * under  the terms of  the GNU General  Public License as published by the

 * Free Software Foundation;  either version 2 of the  License, or (at your

 * option) any later version.

 */



#include <linux/pci.h>



#include <asm/of_platform.h>

#include <asm/time.h>

#include <asm/ipic.h>

#include <asm/udbg.h>

#include <asm/qe.h>

#include <asm/qe_ic.h>



#include "mpc83xx.h"



#undef DEBUG

#ifdef DEBUG

#define DBG(fmt...) udbg_printf(fmt)

#else

#define DBG(fmt...)

#endif



#ifndef CONFIG_PCI

unsigned long isa_io_base = 0;

unsigned long isa_mem_base = 0;

#endif



/* ************************************************************************

 *

 * Setup the architecture

 *

 */

static void __init mpc832x_rdb_setup_arch(void)

{

	struct device_node *np;



	if (ppc_md.progress)

		ppc_md.progress("mpc832x_rdb_setup_arch()", 0);



#ifdef CONFIG_PCI

	for (np = NULL; (np = of_find_node_by_type(np, "pci")) != NULL;)

		add_bridge(np);



	ppc_md.pci_exclude_device = mpc83xx_exclude_device;

#endif



#ifdef CONFIG_QUICC_ENGINE

	qe_reset();



	if ((np = of_find_node_by_name(np, "par_io")) != NULL) {

		par_io_init(np);

		of_node_put(np);



		for (np = NULL; (np = of_find_node_by_name(np, "ucc")) != NULL;)

			par_io_of_config(np);

	}

#endif				/* CONFIG_QUICC_ENGINE */

}



static struct of_device_id mpc832x_ids[] = {

	{ .type = "soc", },

	{ .compatible = "soc", },

	{ .type = "qe", },

	{},

};



static int __init mpc832x_declare_of_platform_devices(void)

{

	if (!machine_is(mpc832x_rdb))

		return 0;



	/* Publish the QE devices */

	of_platform_bus_probe(NULL, mpc832x_ids, NULL);



	return 0;

}

device_initcall(mpc832x_declare_of_platform_devices);



void __init mpc832x_rdb_init_IRQ(void)

{



	struct device_node *np;



	np = of_find_node_by_type(NULL, "ipic");

	if (!np)

		return;



	ipic_init(np, 0);



	/* Initialize the default interrupt mapping priorities,

	 * in case the boot rom changed something on us.

	 */

	ipic_set_default_priority();

	of_node_put(np);



#ifdef CONFIG_QUICC_ENGINE

	np = of_find_node_by_type(NULL, "qeic");

	if (!np)

		return;



	qe_ic_init(np, 0);

	of_node_put(np);

#endif				/* CONFIG_QUICC_ENGINE */

}



/*

 * Called very early, MMU is off, device-tree isn't unflattened

 */

static int __init mpc832x_rdb_probe(void)

{

	unsigned long root = of_get_flat_dt_root();



	return of_flat_dt_is_compatible(root, "MPC832xRDB");

}



define_machine(mpc832x_rdb) {

	.name		= "MPC832x RDB",

	.probe		= mpc832x_rdb_probe,

	.setup_arch	= mpc832x_rdb_setup_arch,

	.init_IRQ	= mpc832x_rdb_init_IRQ,

	.get_irq	= ipic_get_irq,

	.restart	= mpc83xx_restart,

	.time_init	= mpc83xx_time_init,

	.calibrate_decr	= generic_calibrate_decr,

	.progress	= udbg_progress,

};

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