drm/amdgpu: change hw sched list on ctx priority override

	return fence;

}

static void amdgpu_ctx_set_entity_priority(struct amdgpu_ctx *ctx,

					    struct amdgpu_ctx_entity *aentity,

					    int hw_ip,

					    enum drm_sched_priority priority)

{

	struct amdgpu_device *adev = ctx->adev;

	enum gfx_pipe_priority hw_prio;

	struct drm_gpu_scheduler **scheds = NULL;

	unsigned num_scheds;

	/* set sw priority */

	drm_sched_entity_set_priority(&aentity->entity, priority);

	/* set hw priority */

	if (hw_ip == AMDGPU_HW_IP_COMPUTE) {

		hw_prio = amdgpu_ctx_sched_prio_to_compute_prio(priority);

		scheds = adev->gfx.compute_prio_sched[hw_prio];

		num_scheds = adev->gfx.num_compute_sched[hw_prio];

		drm_sched_entity_modify_sched(&aentity->entity, scheds,

					      num_scheds);

	}

}

void amdgpu_ctx_priority_override(struct amdgpu_ctx *ctx,

				  enum drm_sched_priority priority)

{

			ctx->init_priority : ctx->override_priority;

	for (i = 0; i < AMDGPU_HW_IP_NUM; ++i) {

		for (j = 0; j < amdgpu_ctx_num_entities[i]; ++j) {

			struct drm_sched_entity *entity;

			if (!ctx->entities[i][j])

				continue;

			entity = &ctx->entities[i][j]->entity;

			drm_sched_entity_set_priority(entity, ctx_prio);

			amdgpu_ctx_set_entity_priority(ctx, ctx->entities[i][j],

						       i, ctx_prio);

		}

	}

}