Commit 22bc72c8 authored by Dave Airlie's avatar Dave Airlie
Browse files

Merge branch 'drm-next-4.16' of git://people.freedesktop.org/~agd5f/linux into drm-next 

 A few more fixes for 4.16, nothing major.

A few more fixes for 4.16.  This is on top of the pull request from
last week.  Most notable change here is a fix to the link order for
the now separate from amdgpu GPU scheduler to fix crashes when the
modules are build into the kernel rather than as modules.

* 'drm-next-4.16' of git://people.freedesktop.org/~agd5f/linux:
  drm: fix gpu scheduler link order
  drm/amd/display: Demote error print to debug print when ATOM impl missing
  drm/amdgpu: Avoid leaking PM domain on driver unbind (v2)
  drm/amd/amdgpu: Add Polaris version check
  drm/amdgpu: Reenable manual GPU reset from sysfs
  drm/amdgpu: disable MMHUB power gating on raven
  drm/ttm: Don't unreserve swapped BOs that were previously reserved
  drm/ttm: Don't add swapped BOs to swap-LRU list
  drm/amdgpu: only check for ECC on Vega10
  drm/amd/powerplay: Fix smu_table_entry.handle type
  drm/ttm: add VADDR_FLAG_UPDATED_COUNT to correctly update dma_page global count
  drm/radeon: fill in rb backend map on evergreen/ni.
  drm/amdgpu/gfx9: fix ngg enablement to clear gds reserved memory (v2)
  drm/ttm: only free pages rather than update global memory count together
  drm/amdgpu: fix CPU based VM updates
  drm/amdgpu: fix typo in amdgpu_vce_validate_bo
  drm/amdgpu: fix amdgpu_vm_pasid_fault_credit
  drm/ttm: check the return value of register_shrinker
  drm/radeon: fix sparse warning: Should it be static?
parents 92eb5f0c 87440329

drivers/gpu/drm/Makefile

+1 −1
Original line number Diff line number Diff line
@@ -50,6 +50,7 @@ obj-$(CONFIG_DRM_MIPI_DSI) += drm_mipi_dsi.o 
obj-$(CONFIG_DRM_PANEL_ORIENTATION_QUIRKS) += drm_panel_orientation_quirks.o

obj-$(CONFIG_DRM_ARM)	+= arm/

obj-$(CONFIG_DRM_TTM)	+= ttm/

obj-$(CONFIG_DRM_SCHED)	+= scheduler/

obj-$(CONFIG_DRM_TDFX)	+= tdfx/

obj-$(CONFIG_DRM_R128)	+= r128/

obj-y			+= amd/lib/
@@ -102,4 +103,3 @@ obj-$(CONFIG_DRM_MXSFB) += mxsfb/ 
obj-$(CONFIG_DRM_TINYDRM) += tinydrm/

obj-$(CONFIG_DRM_PL111) += pl111/

obj-$(CONFIG_DRM_TVE200) += tve200/
 
obj-$(CONFIG_DRM_SCHED)	+= scheduler/

drivers/gpu/drm/amd/amdgpu/amdgpu_device.c

+1 −3
Original line number Diff line number Diff line
@@ -1874,8 +1874,6 @@ int amdgpu_device_init(struct amdgpu_device *adev, 
	 * ignore it */

	vga_client_register(adev->pdev, adev, NULL, amdgpu_device_vga_set_decode);



	if (amdgpu_runtime_pm == 1)

		runtime = true;

	if (amdgpu_device_is_px(ddev))

		runtime = true;

	if (!pci_is_thunderbolt_attached(adev->pdev))
@@ -2619,7 +2617,7 @@ int amdgpu_device_gpu_recover(struct amdgpu_device *adev, 
	uint64_t reset_flags = 0;

	int i, r, resched;



	if (!amdgpu_device_ip_check_soft_reset(adev)) {

	if (!force && !amdgpu_device_ip_check_soft_reset(adev)) {

		DRM_INFO("No hardware hang detected. Did some blocks stall?\n");

		return 0;

	}

drivers/gpu/drm/amd/amdgpu/amdgpu_vce.c

+2 −2
Original line number Diff line number Diff line
@@ -585,8 +585,8 @@ static int amdgpu_vce_validate_bo(struct amdgpu_cs_parser *p, uint32_t ib_idx, 


	for (i = 0; i < bo->placement.num_placement; ++i) {

		bo->placements[i].fpfn = max(bo->placements[i].fpfn, fpfn);

		bo->placements[i].lpfn = bo->placements[i].fpfn ?

			min(bo->placements[i].fpfn, lpfn) : lpfn;

		bo->placements[i].lpfn = bo->placements[i].lpfn ?

			min(bo->placements[i].lpfn, lpfn) : lpfn;

	}

	return ttm_bo_validate(&bo->tbo, &bo->placement, &ctx);

}

drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c

+16 −8
Original line number Diff line number Diff line
@@ -970,12 +970,16 @@ static void amdgpu_vm_handle_huge_pages(struct amdgpu_pte_update_params *p, 
	amdgpu_gart_get_vm_pde(p->adev, AMDGPU_VM_PDB0,

			       &dst, &flags);



	if (p->func == amdgpu_vm_cpu_set_ptes) {

		pd_addr = (unsigned long)amdgpu_bo_kptr(parent->base.bo);

	} else {

		if (parent->base.bo->shadow) {

			pd_addr = amdgpu_bo_gpu_offset(parent->base.bo->shadow);

			pde = pd_addr + (entry - parent->entries) * 8;

			p->func(p, pde, dst, 1, 0, flags);

		}

		pd_addr = amdgpu_bo_gpu_offset(parent->base.bo);

	}

	pde = pd_addr + (entry - parent->entries) * 8;

	p->func(p, pde, dst, 1, 0, flags);

}
@@ -2478,17 +2482,21 @@ bool amdgpu_vm_pasid_fault_credit(struct amdgpu_device *adev, 


	spin_lock(&adev->vm_manager.pasid_lock);

	vm = idr_find(&adev->vm_manager.pasid_idr, pasid);

	spin_unlock(&adev->vm_manager.pasid_lock);

	if (!vm)

	if (!vm) {

		/* VM not found, can't track fault credit */

		spin_unlock(&adev->vm_manager.pasid_lock);

		return true;

	}



	/* No lock needed. only accessed by IRQ handler */

	if (!vm->fault_credit)

	if (!vm->fault_credit) {

		/* Too many faults in this VM */

		spin_unlock(&adev->vm_manager.pasid_lock);

		return false;

	}



	vm->fault_credit--;

	spin_unlock(&adev->vm_manager.pasid_lock);

	return true;

}

drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c

+5 −4
Original line number Diff line number Diff line
@@ -1068,8 +1068,8 @@ static int gfx_v9_0_ngg_init(struct amdgpu_device *adev) 
	adev->gfx.ngg.gds_reserve_size = ALIGN(5 * 4, 0x40);

	adev->gds.mem.total_size -= adev->gfx.ngg.gds_reserve_size;

	adev->gds.mem.gfx_partition_size -= adev->gfx.ngg.gds_reserve_size;

	adev->gfx.ngg.gds_reserve_addr = SOC15_REG_OFFSET(GC, 0, mmGDS_VMID0_BASE);

	adev->gfx.ngg.gds_reserve_addr += adev->gds.mem.gfx_partition_size;

	adev->gfx.ngg.gds_reserve_addr = RREG32_SOC15(GC, 0, mmGDS_VMID0_BASE);

	adev->gfx.ngg.gds_reserve_addr += RREG32_SOC15(GC, 0, mmGDS_VMID0_SIZE);



	/* Primitive Buffer */

	r = gfx_v9_0_ngg_create_buf(adev, &adev->gfx.ngg.buf[NGG_PRIM],
@@ -1181,13 +1181,14 @@ static int gfx_v9_0_ngg_en(struct amdgpu_device *adev) 


	amdgpu_ring_write(ring, PACKET3(PACKET3_DMA_DATA, 5));

	amdgpu_ring_write(ring, (PACKET3_DMA_DATA_CP_SYNC |

				PACKET3_DMA_DATA_DST_SEL(1) |

				PACKET3_DMA_DATA_SRC_SEL(2)));

	amdgpu_ring_write(ring, 0);

	amdgpu_ring_write(ring, 0);

	amdgpu_ring_write(ring, adev->gfx.ngg.gds_reserve_addr);

	amdgpu_ring_write(ring, 0);

	amdgpu_ring_write(ring, adev->gfx.ngg.gds_reserve_size);



	amdgpu_ring_write(ring, PACKET3_DMA_DATA_CMD_RAW_WAIT |

				adev->gfx.ngg.gds_reserve_size);



	gfx_v9_0_write_data_to_reg(ring, 0, false,

				   SOC15_REG_OFFSET(GC, 0, mmGDS_VMID0_SIZE), 0);

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