Commit 229b969b authored Jul 14, 2019 by Andy Lutomirski Committed by Thomas Gleixner Jul 22, 2019

x86/apic: Initialize TPR to block interrupts 16-31

The APIC, per spec, is fundamentally confused and thinks that interrupt
vectors 16-31 are valid. This makes no sense -- the CPU reserves vectors
0-31 for exceptions (faults, traps, etc). Obviously, no device should
actually produce an interrupt with vector 16-31, but robustness can be
improved by setting the APIC TPR class to 1, which will prevent delivery of
an interrupt with a vector below 32.

Note: This is *not* intended as a security measure against attackers who
control malicious hardware. Any PCI or similar hardware that can be
controlled by an attacker MUST be behind a functional IOMMU that remaps
interrupts. The purpose of this change is to reduce the chance that a
certain class of device malfunctions crashes the kernel in hard-to-debug
ways.

Suggested-by: Andrew Cooper <andrew.cooper3@citrix.com>
Signed-off-by: Andy Lutomirski <luto@kernel.org>
Signed-off-by: Thomas Gleixner <tglx@linutronix.de>
Link: https://lkml.kernel.org/r/dc04a9f8b234d7b0956a8d2560b8945bcd9c4bf7.1563117760.git.luto@kernel.org

parent 5f9e832c

arch/x86/kernel/apic/apic.c

+5 −2

Original line number	Diff line number	Diff line
		@@ -1561,11 +1561,14 @@ static void setup_local_APIC(void)
		#endif

		/*
		* Set Task Priority to 'accept all'. We never change this
		* later on.
		* Set Task Priority to 'accept all except vectors 0-31'. An APIC
		* vector in the 16-31 range could be delivered if TPR == 0, but we
		* would think it's an exception and terrible things will happen. We
		* never change this later on.
		*/
		value = apic_read(APIC_TASKPRI);
		value &= ~APIC_TPRI_MASK;
		value \|= 0x10;
		apic_write(APIC_TASKPRI, value);

		apic_pending_intr_clear();

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