Commit 227fab90 authored by Krishna Gudipati's avatar Krishna Gudipati Committed by James Bottomley
Browse files

[SCSI] bfa: Flash Controller PLL initialization fixes 



- Made changes to check the flash controller status before IOC initialization.
- Made changes to poll on the FLASH_STS_REG bit to check if the flash controller
  initialization is completed during the PLL init.

Signed-off-by: default avatarVijaya Mohan Guvva <vmohan@brocade.com>
Signed-off-by: default avatarKrishna Gudipati <kgudipat@brocade.com>
Signed-off-by: default avatarJames Bottomley <JBottomley@Parallels.com>
parent 7ac83b1f

drivers/scsi/bfa/bfa_ioc_ct.c

+128 −83
Original line number Diff line number Diff line
@@ -744,25 +744,6 @@ bfa_ioc_ct2_mem_init(void __iomem *rb) 
void

bfa_ioc_ct2_mac_reset(void __iomem *rb)

{

	u32	r32;



	bfa_ioc_ct2_sclk_init(rb);

	bfa_ioc_ct2_lclk_init(rb);



	/*

	 * release soft reset on s_clk & l_clk

	 */

	r32 = readl((rb + CT2_APP_PLL_SCLK_CTL_REG));

	writel(r32 & ~__APP_PLL_SCLK_LOGIC_SOFT_RESET,

		(rb + CT2_APP_PLL_SCLK_CTL_REG));



	/*

	 * release soft reset on s_clk & l_clk

	 */

	r32 = readl((rb + CT2_APP_PLL_LCLK_CTL_REG));

	writel(r32 & ~__APP_PLL_LCLK_LOGIC_SOFT_RESET,

		(rb + CT2_APP_PLL_LCLK_CTL_REG));



	/* put port0, port1 MAC & AHB in reset */

	writel((__CSI_MAC_RESET | __CSI_MAC_AHB_RESET),

		rb + CT2_CSI_MAC_CONTROL_REG(0));
@@ -770,8 +751,21 @@ bfa_ioc_ct2_mac_reset(void __iomem *rb) 
		rb + CT2_CSI_MAC_CONTROL_REG(1));

}



static void

bfa_ioc_ct2_enable_flash(void __iomem *rb)

{

	u32 r32;



	r32 = readl((rb + PSS_GPIO_OUT_REG));

	writel(r32 & ~1, (rb + PSS_GPIO_OUT_REG));

	r32 = readl((rb + PSS_GPIO_OE_REG));

	writel(r32 | 1, (rb + PSS_GPIO_OE_REG));

}



#define CT2_NFC_MAX_DELAY	1000

#define CT2_NFC_VER_VALID	0x143

#define CT2_NFC_PAUSE_MAX_DELAY 4000

#define CT2_NFC_VER_VALID	0x147

#define CT2_NFC_STATE_RUNNING   0x20000001

#define BFA_IOC_PLL_POLL	1000000



static bfa_boolean_t
@@ -786,6 +780,20 @@ bfa_ioc_ct2_nfc_halted(void __iomem *rb) 
	return BFA_FALSE;

}



static void

bfa_ioc_ct2_nfc_halt(void __iomem *rb)

{

	int	i;



	writel(__HALT_NFC_CONTROLLER, rb + CT2_NFC_CSR_SET_REG);

	for (i = 0; i < CT2_NFC_MAX_DELAY; i++) {

		if (bfa_ioc_ct2_nfc_halted(rb))

			break;

		udelay(1000);

	}

	WARN_ON(!bfa_ioc_ct2_nfc_halted(rb));

}



static void

bfa_ioc_ct2_nfc_resume(void __iomem *rb)

{
@@ -802,105 +810,142 @@ bfa_ioc_ct2_nfc_resume(void __iomem *rb) 
	WARN_ON(1);

}



bfa_status_t

bfa_ioc_ct2_pll_init(void __iomem *rb, enum bfi_asic_mode mode)

static void

bfa_ioc_ct2_clk_reset(void __iomem *rb)

{

	u32 wgn, r32, nfc_ver, i;

	u32 r32;



	wgn = readl(rb + CT2_WGN_STATUS);

	nfc_ver = readl(rb + CT2_RSC_GPR15_REG);

	bfa_ioc_ct2_sclk_init(rb);

	bfa_ioc_ct2_lclk_init(rb);



	if ((wgn == (__A2T_AHB_LOAD | __WGN_READY)) &&

	    (nfc_ver >= CT2_NFC_VER_VALID)) {

		if (bfa_ioc_ct2_nfc_halted(rb))

			bfa_ioc_ct2_nfc_resume(rb);

	/*

	 * release soft reset on s_clk & l_clk

	 */

	r32 = readl((rb + CT2_APP_PLL_SCLK_CTL_REG));

	writel(r32 & ~__APP_PLL_SCLK_LOGIC_SOFT_RESET,

			(rb + CT2_APP_PLL_SCLK_CTL_REG));



		writel(__RESET_AND_START_SCLK_LCLK_PLLS,

		       rb + CT2_CSI_FW_CTL_SET_REG);

	r32 = readl((rb + CT2_APP_PLL_LCLK_CTL_REG));

	writel(r32 & ~__APP_PLL_LCLK_LOGIC_SOFT_RESET,

			(rb + CT2_APP_PLL_LCLK_CTL_REG));



		for (i = 0; i < BFA_IOC_PLL_POLL; i++) {

			r32 = readl(rb + CT2_APP_PLL_LCLK_CTL_REG);

			if (r32 & __RESET_AND_START_SCLK_LCLK_PLLS)

				break;

}



		WARN_ON(!(r32 & __RESET_AND_START_SCLK_LCLK_PLLS));

static void

bfa_ioc_ct2_nfc_clk_reset(void __iomem *rb)

{

	u32 r32, i;



	r32 = readl((rb + PSS_CTL_REG));

	r32 |= (__PSS_LPU0_RESET | __PSS_LPU1_RESET);

	writel(r32, (rb + PSS_CTL_REG));



	writel(__RESET_AND_START_SCLK_LCLK_PLLS, rb + CT2_CSI_FW_CTL_SET_REG);



	for (i = 0; i < BFA_IOC_PLL_POLL; i++) {

			r32 = readl(rb + CT2_APP_PLL_LCLK_CTL_REG);

			if (!(r32 & __RESET_AND_START_SCLK_LCLK_PLLS))

		r32 = readl(rb + CT2_NFC_FLASH_STS_REG);



		if ((r32 & __FLASH_PLL_INIT_AND_RESET_IN_PROGRESS))

			break;

	}

	WARN_ON(!(r32 & __FLASH_PLL_INIT_AND_RESET_IN_PROGRESS));



		WARN_ON(r32 & __RESET_AND_START_SCLK_LCLK_PLLS);

		udelay(1000);

	for (i = 0; i < BFA_IOC_PLL_POLL; i++) {

		r32 = readl(rb + CT2_NFC_FLASH_STS_REG);



		r32 = readl(rb + CT2_CSI_FW_CTL_REG);

		WARN_ON(r32 & __RESET_AND_START_SCLK_LCLK_PLLS);

	} else {

		writel(__HALT_NFC_CONTROLLER, rb + CT2_NFC_CSR_SET_REG);

		for (i = 0; i < CT2_NFC_MAX_DELAY; i++) {

			r32 = readl(rb + CT2_NFC_CSR_SET_REG);

			if (r32 & __NFC_CONTROLLER_HALTED)

		if (!(r32 & __FLASH_PLL_INIT_AND_RESET_IN_PROGRESS))

			break;

			udelay(1000);

	}

	WARN_ON((r32 & __FLASH_PLL_INIT_AND_RESET_IN_PROGRESS));



		bfa_ioc_ct2_mac_reset(rb);

		bfa_ioc_ct2_sclk_init(rb);

		bfa_ioc_ct2_lclk_init(rb);

	r32 = readl(rb + CT2_CSI_FW_CTL_REG);

	WARN_ON((r32 & __RESET_AND_START_SCLK_LCLK_PLLS));

}



		/*

		 * release soft reset on s_clk & l_clk

		 */

		r32 = readl(rb + CT2_APP_PLL_SCLK_CTL_REG);

		writel(r32 & ~__APP_PLL_SCLK_LOGIC_SOFT_RESET,

		       (rb + CT2_APP_PLL_SCLK_CTL_REG));

static void

bfa_ioc_ct2_wait_till_nfc_running(void __iomem *rb)

{

	u32 r32;

	int i;



		/*

		 * release soft reset on s_clk & l_clk

		 */

		r32 = readl(rb + CT2_APP_PLL_LCLK_CTL_REG);

		writel(r32 & ~__APP_PLL_LCLK_LOGIC_SOFT_RESET,

		      (rb + CT2_APP_PLL_LCLK_CTL_REG));

	if (bfa_ioc_ct2_nfc_halted(rb))

		bfa_ioc_ct2_nfc_resume(rb);

	for (i = 0; i < CT2_NFC_PAUSE_MAX_DELAY; i++) {

		r32 = readl(rb + CT2_NFC_STS_REG);

		if (r32 == CT2_NFC_STATE_RUNNING)

			return;

		udelay(1000);

	}



	r32 = readl(rb + CT2_NFC_STS_REG);

	WARN_ON(!(r32 == CT2_NFC_STATE_RUNNING));

}



bfa_status_t

bfa_ioc_ct2_pll_init(void __iomem *rb, enum bfi_asic_mode mode)

{

	u32 wgn, r32, nfc_ver;



	wgn = readl(rb + CT2_WGN_STATUS);



	if (wgn == (__WGN_READY | __GLBL_PF_VF_CFG_RDY)) {

		/*

	 * Announce flash device presence, if flash was corrupted.

		 * If flash is corrupted, enable flash explicitly

		 */

	if (wgn == (__WGN_READY | __GLBL_PF_VF_CFG_RDY)) {

		r32 = readl(rb + PSS_GPIO_OUT_REG);

		writel(r32 & ~1, (rb + PSS_GPIO_OUT_REG));

		r32 = readl(rb + PSS_GPIO_OE_REG);

		writel(r32 | 1, (rb + PSS_GPIO_OE_REG));

		bfa_ioc_ct2_clk_reset(rb);

		bfa_ioc_ct2_enable_flash(rb);



		bfa_ioc_ct2_mac_reset(rb);



		bfa_ioc_ct2_clk_reset(rb);

		bfa_ioc_ct2_enable_flash(rb);



	} else {

		nfc_ver = readl(rb + CT2_RSC_GPR15_REG);



		if ((nfc_ver >= CT2_NFC_VER_VALID) &&

		    (wgn == (__A2T_AHB_LOAD | __WGN_READY))) {



			bfa_ioc_ct2_wait_till_nfc_running(rb);



			bfa_ioc_ct2_nfc_clk_reset(rb);

		} else {

			bfa_ioc_ct2_nfc_halt(rb);



			bfa_ioc_ct2_clk_reset(rb);

			bfa_ioc_ct2_mac_reset(rb);

			bfa_ioc_ct2_clk_reset(rb);



		}

	}



	/*

	 * Mask the interrupts and clear any

	 * pending interrupts.

	 * pending interrupts left by BIOS/EFI

	 */



	writel(1, (rb + CT2_LPU0_HOSTFN_MBOX0_MSK));

	writel(1, (rb + CT2_LPU1_HOSTFN_MBOX0_MSK));



	/* For first time initialization, no need to clear interrupts */

	r32 = readl(rb + HOST_SEM5_REG);

	if (r32 & 0x1) {

		r32 = readl(rb + CT2_LPU0_HOSTFN_CMD_STAT);

		r32 = readl((rb + CT2_LPU0_HOSTFN_CMD_STAT));

		if (r32 == 1) {

			writel(1, rb + CT2_LPU0_HOSTFN_CMD_STAT);

			writel(1, (rb + CT2_LPU0_HOSTFN_CMD_STAT));

			readl((rb + CT2_LPU0_HOSTFN_CMD_STAT));

		}

		r32 = readl(rb + CT2_LPU1_HOSTFN_CMD_STAT);

		r32 = readl((rb + CT2_LPU1_HOSTFN_CMD_STAT));

		if (r32 == 1) {

			writel(1, rb + CT2_LPU1_HOSTFN_CMD_STAT);

			readl(rb + CT2_LPU1_HOSTFN_CMD_STAT);

			writel(1, (rb + CT2_LPU1_HOSTFN_CMD_STAT));

			readl((rb + CT2_LPU1_HOSTFN_CMD_STAT));

		}

	}



	bfa_ioc_ct2_mem_init(rb);



	writel(BFI_IOC_UNINIT, rb + CT2_BFA_IOC0_STATE_REG);

	writel(BFI_IOC_UNINIT, rb + CT2_BFA_IOC1_STATE_REG);

	writel(BFI_IOC_UNINIT, (rb + CT2_BFA_IOC0_STATE_REG));

	writel(BFI_IOC_UNINIT, (rb + CT2_BFA_IOC1_STATE_REG));



	return BFA_STATUS_OK;

}

drivers/scsi/bfa/bfi_reg.h

+3 −0
Original line number Diff line number Diff line
@@ -338,6 +338,7 @@ enum { 
#define __A2T_AHB_LOAD			0x00000800

#define __WGN_READY			0x00000400

#define __GLBL_PF_VF_CFG_RDY		0x00000200

#define CT2_NFC_STS_REG			0x00027410

#define CT2_NFC_CSR_CLR_REG		0x00027420

#define CT2_NFC_CSR_SET_REG		0x00027424

#define __HALT_NFC_CONTROLLER		0x00000002
@@ -355,6 +356,8 @@ enum { 
	(CT2_CSI_MAC0_CONTROL_REG +	\

	(__n) * (CT2_CSI_MAC1_CONTROL_REG - CT2_CSI_MAC0_CONTROL_REG))



#define CT2_NFC_FLASH_STS_REG		0x00014834

#define __FLASH_PLL_INIT_AND_RESET_IN_PROGRESS	0x00000020

/*

 * Name semaphore registers based on usage

 */

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