Commit 227f7d58 authored by Kenneth Feng's avatar Kenneth Feng Committed by Alex Deucher
Browse files

drm/amd/amdgpu: add IH cg support on soc15 project 



enable/disable IH clock gating on soc15 projects.

Signed-off-by: default avatarKenneth Feng <kenneth.feng@amd.com>
Reviewed-by: default avatarKevin Wang <kevin1.wang@amd.com>
Signed-off-by: default avatarAlex Deucher <alexander.deucher@amd.com>
parent 95f71bfa

drivers/gpu/drm/amd/amdgpu/soc15.c

+2 −1
Original line number Diff line number Diff line
@@ -1170,7 +1170,8 @@ static int soc15_common_early_init(void *handle) 
			AMD_CG_SUPPORT_SDMA_MGCG |

			AMD_CG_SUPPORT_SDMA_LS |

			AMD_CG_SUPPORT_MC_MGCG |

			AMD_CG_SUPPORT_MC_LS;

			AMD_CG_SUPPORT_MC_LS |

			AMD_CG_SUPPORT_IH_CG;

		adev->pg_flags = 0;

		adev->external_rev_id = adev->rev_id + 0x32;

		break;

drivers/gpu/drm/amd/amdgpu/vega10_ih.c

+39 −0
Original line number Diff line number Diff line
@@ -675,10 +675,49 @@ static int vega10_ih_soft_reset(void *handle) 
	return 0;

}



static void vega10_ih_update_clockgating_state(struct amdgpu_device *adev,

					       bool enable)

{

	uint32_t data, def, field_val;



	if (adev->cg_flags & AMD_CG_SUPPORT_IH_CG) {

		def = data = RREG32_SOC15(OSSSYS, 0, mmIH_CLK_CTRL);

		field_val = enable ? 0 : 1;

		/**

		 * Vega10 does not have IH_RETRY_INT_CAM_MEM_CLK_SOFT_OVERRIDE

		 * and IH_BUFFER_MEM_CLK_SOFT_OVERRIDE field.

		 */

		if (adev->asic_type > CHIP_VEGA10) {

			data = REG_SET_FIELD(data, IH_CLK_CTRL,

				     IH_RETRY_INT_CAM_MEM_CLK_SOFT_OVERRIDE, field_val);

			data = REG_SET_FIELD(data, IH_CLK_CTRL,

				     IH_BUFFER_MEM_CLK_SOFT_OVERRIDE, field_val);

		}



		data = REG_SET_FIELD(data, IH_CLK_CTRL,

				     DBUS_MUX_CLK_SOFT_OVERRIDE, field_val);

		data = REG_SET_FIELD(data, IH_CLK_CTRL,

				     OSSSYS_SHARE_CLK_SOFT_OVERRIDE, field_val);

		data = REG_SET_FIELD(data, IH_CLK_CTRL,

				     LIMIT_SMN_CLK_SOFT_OVERRIDE, field_val);

		data = REG_SET_FIELD(data, IH_CLK_CTRL,

				     DYN_CLK_SOFT_OVERRIDE, field_val);

		data = REG_SET_FIELD(data, IH_CLK_CTRL,

				     REG_CLK_SOFT_OVERRIDE, field_val);

		if (def != data)

			WREG32_SOC15(OSSSYS, 0, mmIH_CLK_CTRL, data);

	}

}



static int vega10_ih_set_clockgating_state(void *handle,

					  enum amd_clockgating_state state)

{

	struct amdgpu_device *adev = (struct amdgpu_device *)handle;



	vega10_ih_update_clockgating_state(adev,

				state == AMD_CG_STATE_GATE ? true : false);

	return 0;



}



static int vega10_ih_set_powergating_state(void *handle,

drivers/gpu/drm/amd/include/asic_reg/oss/osssys_4_0_sh_mask.h

+4 −0
Original line number Diff line number Diff line
@@ -588,11 +588,15 @@ 
#define IH_STORM_CLIENT_LIST_CNTL__CLIENT30_IS_STORM_CLIENT_MASK                                              0x40000000L

#define IH_STORM_CLIENT_LIST_CNTL__CLIENT31_IS_STORM_CLIENT_MASK                                              0x80000000L

//IH_CLK_CTRL

#define IH_CLK_CTRL__IH_RETRY_INT_CAM_MEM_CLK_SOFT_OVERRIDE__SHIFT                                             0x19

#define IH_CLK_CTRL__IH_BUFFER_MEM_CLK_SOFT_OVERRIDE__SHIFT                                             		  0x1a

#define IH_CLK_CTRL__DBUS_MUX_CLK_SOFT_OVERRIDE__SHIFT                                                        0x1b

#define IH_CLK_CTRL__OSSSYS_SHARE_CLK_SOFT_OVERRIDE__SHIFT                                                    0x1c

#define IH_CLK_CTRL__LIMIT_SMN_CLK_SOFT_OVERRIDE__SHIFT                                                       0x1d

#define IH_CLK_CTRL__DYN_CLK_SOFT_OVERRIDE__SHIFT                                                             0x1e

#define IH_CLK_CTRL__REG_CLK_SOFT_OVERRIDE__SHIFT                                                             0x1f

#define IH_CLK_CTRL__IH_RETRY_INT_CAM_MEM_CLK_SOFT_OVERRIDE_MASK                                              0x02000000L

#define IH_CLK_CTRL__IH_BUFFER_MEM_CLK_SOFT_OVERRIDE_MASK                                             		  0x04000000L

#define IH_CLK_CTRL__DBUS_MUX_CLK_SOFT_OVERRIDE_MASK                                                          0x08000000L

#define IH_CLK_CTRL__OSSSYS_SHARE_CLK_SOFT_OVERRIDE_MASK                                                      0x10000000L

#define IH_CLK_CTRL__LIMIT_SMN_CLK_SOFT_OVERRIDE_MASK                                                         0x20000000L

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