Commit 2255d7f3 authored by James Zhu's avatar James Zhu Committed by Alex Deucher
Browse files

drm/amdgpu/gfx: Clear more EDC cnt 



Clear SDMA and HDP EDC counter in GPR workarounds.

Signed-off-by: default avatarJames Zhu <James.Zhu@amd.com>
Reviewed-by: default avatarHawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: default avatarAlex Deucher <alexander.deucher@amd.com>
parent 858054f7

drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c

+5 −0
Original line number Diff line number Diff line
@@ -48,6 +48,8 @@ 


#include "amdgpu_ras.h"



#include "sdma0/sdma0_4_0_offset.h"

#include "sdma1/sdma1_4_0_offset.h"

#define GFX9_NUM_GFX_RINGS     1

#define GFX9_MEC_HPD_SIZE 4096

#define RLCG_UCODE_LOADING_START_ADDRESS 0x00002000L
@@ -4029,6 +4031,9 @@ static const struct soc15_reg_entry sec_ded_counter_registers[] = { 
   { SOC15_REG_ENTRY(GC, 0, mmTCC_EDC_CNT2), 0, 1, 16},

   { SOC15_REG_ENTRY(GC, 0, mmTCA_EDC_CNT), 0, 1, 2},

   { SOC15_REG_ENTRY(GC, 0, mmSQC_EDC_CNT3), 0, 4, 6},

   { SOC15_REG_ENTRY(SDMA0, 0, mmSDMA0_EDC_COUNTER), 0, 1, 1},

   { SOC15_REG_ENTRY(SDMA1, 0, mmSDMA1_EDC_COUNTER), 0, 1, 1},

   { SOC15_REG_ENTRY(HDP, 0, mmHDP_EDC_CNT), 0, 1, 1},

};



static int gfx_v9_0_do_edc_gds_workarounds(struct amdgpu_device *adev)

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