Commit 22292b91 authored by Tony Lindgren's avatar Tony Lindgren
Browse files

Merge tag 'for-v4.7/omap-hwmod-a' of... 

Merge tag 'for-v4.7/omap-hwmod-a' of git://git.kernel.org/pub/scm/linux/kernel/git/pjw/omap-pending into omap-for-v4.7/soc

ARM: OMAP2+: first set of hwmod changes for v4.7

For the DRA7xx platform, add IP block data for the McASP, PWMSS,
and GPTimer12 IP blocks.  Add lock and unlock functions for the
RTC IP blocks on the DRA7xx, AM33xx, and AM43xx devices.  And add
a fix for the hwmod core for device driver unbind operations for
IP blocks with hardreset lines.

Basic build, boot, and PM test results are available here:

http://www.pwsan.com/omap/testlogs/omap-hwmod-a-for-v4.7/20160410132119/

Note that the testbed here does not have the DRA7xx board included yet.
parents 814a9586 c20c8f75

arch/arm/mach-omap2/clockdomains7xx_data.c

+1 −1
Original line number Diff line number Diff line
@@ -461,7 +461,7 @@ static struct clockdomain ipu_7xx_clkdm = { 
	.cm_inst	  = DRA7XX_CM_CORE_AON_IPU_INST,

	.clkdm_offs	  = DRA7XX_CM_CORE_AON_IPU_IPU_CDOFFS,

	.dep_bit	  = DRA7XX_IPU_STATDEP_SHIFT,

	.flags		  = CLKDM_CAN_HWSUP_SWSUP,

	.flags		  = CLKDM_CAN_SWSUP,

};



static struct clockdomain mpu1_7xx_clkdm = {

arch/arm/mach-omap2/omap_hwmod.c

+10 −10
Original line number Diff line number Diff line
@@ -1416,8 +1416,6 @@ static void _enable_sysc(struct omap_hwmod *oh) 
	    (sf & SYSC_HAS_CLOCKACTIVITY))

		_set_clockactivity(oh, oh->class->sysc->clockact, &v);



	/* If the cached value is the same as the new value, skip the write */

	if (oh->_sysc_cache != v)

	_write_sysconfig(v, oh);



	/*
@@ -1481,6 +1479,8 @@ static void _idle_sysc(struct omap_hwmod *oh) 
		_set_master_standbymode(oh, idlemode, &v);

	}



	/* If the cached value is the same as the new value, skip the write */

	if (oh->_sysc_cache != v)

		_write_sysconfig(v, oh);

}
@@ -2207,15 +2207,15 @@ static int _idle(struct omap_hwmod *oh) 


	pr_debug("omap_hwmod: %s: idling\n", oh->name);



	if (_are_all_hardreset_lines_asserted(oh))

		return 0;



	if (oh->_state != _HWMOD_STATE_ENABLED) {

		WARN(1, "omap_hwmod: %s: idle state can only be entered from enabled state\n",

			oh->name);

		return -EINVAL;

	}



	if (_are_all_hardreset_lines_asserted(oh))

		return 0;



	if (oh->class->sysc)

		_idle_sysc(oh);

	_del_initiator_dep(oh, mpu_oh);
@@ -2262,6 +2262,9 @@ static int _shutdown(struct omap_hwmod *oh) 
	int ret, i;

	u8 prev_state;



	if (_are_all_hardreset_lines_asserted(oh))

		return 0;



	if (oh->_state != _HWMOD_STATE_IDLE &&

	    oh->_state != _HWMOD_STATE_ENABLED) {

		WARN(1, "omap_hwmod: %s: disabled state can only be entered from idle, or enabled state\n",
@@ -2269,9 +2272,6 @@ static int _shutdown(struct omap_hwmod *oh) 
		return -EINVAL;

	}



	if (_are_all_hardreset_lines_asserted(oh))

		return 0;



	pr_debug("omap_hwmod: %s: disabling\n", oh->name);



	if (oh->class->pre_shutdown) {

arch/arm/mach-omap2/omap_hwmod.h

+2 −0
Original line number Diff line number Diff line
@@ -754,6 +754,8 @@ const char *omap_hwmod_get_main_clk(struct omap_hwmod *oh); 
 */



extern int omap_hwmod_aess_preprogram(struct omap_hwmod *oh);

void omap_hwmod_rtc_unlock(struct omap_hwmod *oh);

void omap_hwmod_rtc_lock(struct omap_hwmod *oh);



/*

 * Chip variant-specific hwmod init routines - XXX should be converted

arch/arm/mach-omap2/omap_hwmod_33xx_43xx_ipblock_data.c

+2 −0
Original line number Diff line number Diff line
@@ -918,6 +918,8 @@ static struct omap_hwmod_class_sysconfig am33xx_rtc_sysc = { 
static struct omap_hwmod_class am33xx_rtc_hwmod_class = {

	.name		= "rtc",

	.sysc		= &am33xx_rtc_sysc,

	.unlock		= &omap_hwmod_rtc_unlock,

	.lock		= &omap_hwmod_rtc_lock,

};



struct omap_hwmod am33xx_rtc_hwmod = {

arch/arm/mach-omap2/omap_hwmod_7xx_data.c

+362 −2
Original line number Diff line number Diff line
@@ -383,6 +383,68 @@ static struct omap_hwmod dra7xx_dcan2_hwmod = { 
	},

};



/* pwmss  */

static struct omap_hwmod_class_sysconfig dra7xx_epwmss_sysc = {

	.rev_offs	= 0x0,

	.sysc_offs	= 0x4,

	.sysc_flags	= SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET,

	.idlemodes	= (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),

	.sysc_fields	= &omap_hwmod_sysc_type2,

};



/*

 * epwmss class

 */

static struct omap_hwmod_class dra7xx_epwmss_hwmod_class = {

	.name		= "epwmss",

	.sysc		= &dra7xx_epwmss_sysc,

};



/* epwmss0 */

static struct omap_hwmod dra7xx_epwmss0_hwmod = {

	.name		= "epwmss0",

	.class		= &dra7xx_epwmss_hwmod_class,

	.clkdm_name	= "l4per2_clkdm",

	.main_clk	= "l4_root_clk_div",

	.prcm		= {

		.omap4	= {

			.modulemode	= MODULEMODE_SWCTRL,

			.clkctrl_offs	= DRA7XX_CM_L4PER2_PWMSS1_CLKCTRL_OFFSET,

			.context_offs	= DRA7XX_RM_L4PER2_PWMSS1_CONTEXT_OFFSET,

		},

	},

};



/* epwmss1 */

static struct omap_hwmod dra7xx_epwmss1_hwmod = {

	.name		= "epwmss1",

	.class		= &dra7xx_epwmss_hwmod_class,

	.clkdm_name	= "l4per2_clkdm",

	.main_clk	= "l4_root_clk_div",

	.prcm		= {

		.omap4	= {

			.modulemode	= MODULEMODE_SWCTRL,

			.clkctrl_offs	= DRA7XX_CM_L4PER2_PWMSS2_CLKCTRL_OFFSET,

			.context_offs	= DRA7XX_RM_L4PER2_PWMSS2_CONTEXT_OFFSET,

		},

	},

};



/* epwmss2 */

static struct omap_hwmod dra7xx_epwmss2_hwmod = {

	.name		= "epwmss2",

	.class		= &dra7xx_epwmss_hwmod_class,

	.clkdm_name	= "l4per2_clkdm",

	.main_clk	= "l4_root_clk_div",

	.prcm		= {

		.omap4	= {

			.modulemode	= MODULEMODE_SWCTRL,

			.clkctrl_offs	= DRA7XX_CM_L4PER2_PWMSS3_CLKCTRL_OFFSET,

			.context_offs	= DRA7XX_RM_L4PER2_PWMSS3_CONTEXT_OFFSET,

		},

	},

};



/*

 * 'dma' class

 *
@@ -1374,6 +1436,52 @@ static struct omap_hwmod_class dra7xx_mcasp_hwmod_class = { 
	.sysc	= &dra7xx_mcasp_sysc,

};



/* mcasp1 */

static struct omap_hwmod_opt_clk mcasp1_opt_clks[] = {

	{ .role = "ahclkx", .clk = "mcasp1_ahclkx_mux" },

	{ .role = "ahclkr", .clk = "mcasp1_ahclkr_mux" },

};



static struct omap_hwmod dra7xx_mcasp1_hwmod = {

	.name		= "mcasp1",

	.class		= &dra7xx_mcasp_hwmod_class,

	.clkdm_name	= "ipu_clkdm",

	.main_clk	= "mcasp1_aux_gfclk_mux",

	.flags		= HWMOD_OPT_CLKS_NEEDED,

	.prcm = {

		.omap4 = {

			.clkctrl_offs = DRA7XX_CM_IPU_MCASP1_CLKCTRL_OFFSET,

			.context_offs = DRA7XX_RM_IPU_MCASP1_CONTEXT_OFFSET,

			.modulemode   = MODULEMODE_SWCTRL,

		},

	},

	.opt_clks	= mcasp1_opt_clks,

	.opt_clks_cnt	= ARRAY_SIZE(mcasp1_opt_clks),

};



/* mcasp2 */

static struct omap_hwmod_opt_clk mcasp2_opt_clks[] = {

	{ .role = "ahclkx", .clk = "mcasp2_ahclkx_mux" },

	{ .role = "ahclkr", .clk = "mcasp2_ahclkr_mux" },

};



static struct omap_hwmod dra7xx_mcasp2_hwmod = {

	.name		= "mcasp2",

	.class		= &dra7xx_mcasp_hwmod_class,

	.clkdm_name	= "l4per2_clkdm",

	.main_clk	= "mcasp2_aux_gfclk_mux",

	.flags		= HWMOD_OPT_CLKS_NEEDED,

	.prcm = {

		.omap4 = {

			.clkctrl_offs = DRA7XX_CM_L4PER2_MCASP2_CLKCTRL_OFFSET,

			.context_offs = DRA7XX_RM_L4PER2_MCASP2_CONTEXT_OFFSET,

			.modulemode   = MODULEMODE_SWCTRL,

		},

	},

	.opt_clks	= mcasp2_opt_clks,

	.opt_clks_cnt	= ARRAY_SIZE(mcasp2_opt_clks),

};



/* mcasp3 */

static struct omap_hwmod_opt_clk mcasp3_opt_clks[] = {

	{ .role = "ahclkx", .clk = "mcasp3_ahclkx_mux" },
@@ -1396,6 +1504,116 @@ static struct omap_hwmod dra7xx_mcasp3_hwmod = { 
	.opt_clks_cnt	= ARRAY_SIZE(mcasp3_opt_clks),

};



/* mcasp4 */

static struct omap_hwmod_opt_clk mcasp4_opt_clks[] = {

	{ .role = "ahclkx", .clk = "mcasp4_ahclkx_mux" },

};



static struct omap_hwmod dra7xx_mcasp4_hwmod = {

	.name		= "mcasp4",

	.class		= &dra7xx_mcasp_hwmod_class,

	.clkdm_name	= "l4per2_clkdm",

	.main_clk	= "mcasp4_aux_gfclk_mux",

	.flags		= HWMOD_OPT_CLKS_NEEDED,

	.prcm = {

		.omap4 = {

			.clkctrl_offs = DRA7XX_CM_L4PER2_MCASP4_CLKCTRL_OFFSET,

			.context_offs = DRA7XX_RM_L4PER2_MCASP4_CONTEXT_OFFSET,

			.modulemode   = MODULEMODE_SWCTRL,

		},

	},

	.opt_clks	= mcasp4_opt_clks,

	.opt_clks_cnt	= ARRAY_SIZE(mcasp4_opt_clks),

};



/* mcasp5 */

static struct omap_hwmod_opt_clk mcasp5_opt_clks[] = {

	{ .role = "ahclkx", .clk = "mcasp5_ahclkx_mux" },

};



static struct omap_hwmod dra7xx_mcasp5_hwmod = {

	.name		= "mcasp5",

	.class		= &dra7xx_mcasp_hwmod_class,

	.clkdm_name	= "l4per2_clkdm",

	.main_clk	= "mcasp5_aux_gfclk_mux",

	.flags		= HWMOD_OPT_CLKS_NEEDED,

	.prcm = {

		.omap4 = {

			.clkctrl_offs = DRA7XX_CM_L4PER2_MCASP5_CLKCTRL_OFFSET,

			.context_offs = DRA7XX_RM_L4PER2_MCASP5_CONTEXT_OFFSET,

			.modulemode   = MODULEMODE_SWCTRL,

		},

	},

	.opt_clks	= mcasp5_opt_clks,

	.opt_clks_cnt	= ARRAY_SIZE(mcasp5_opt_clks),

};



/* mcasp6 */

static struct omap_hwmod_opt_clk mcasp6_opt_clks[] = {

	{ .role = "ahclkx", .clk = "mcasp6_ahclkx_mux" },

};



static struct omap_hwmod dra7xx_mcasp6_hwmod = {

	.name		= "mcasp6",

	.class		= &dra7xx_mcasp_hwmod_class,

	.clkdm_name	= "l4per2_clkdm",

	.main_clk	= "mcasp6_aux_gfclk_mux",

	.flags		= HWMOD_OPT_CLKS_NEEDED,

	.prcm = {

		.omap4 = {

			.clkctrl_offs = DRA7XX_CM_L4PER2_MCASP6_CLKCTRL_OFFSET,

			.context_offs = DRA7XX_RM_L4PER2_MCASP6_CONTEXT_OFFSET,

			.modulemode   = MODULEMODE_SWCTRL,

		},

	},

	.opt_clks	= mcasp6_opt_clks,

	.opt_clks_cnt	= ARRAY_SIZE(mcasp6_opt_clks),

};



/* mcasp7 */

static struct omap_hwmod_opt_clk mcasp7_opt_clks[] = {

	{ .role = "ahclkx", .clk = "mcasp7_ahclkx_mux" },

};



static struct omap_hwmod dra7xx_mcasp7_hwmod = {

	.name		= "mcasp7",

	.class		= &dra7xx_mcasp_hwmod_class,

	.clkdm_name	= "l4per2_clkdm",

	.main_clk	= "mcasp7_aux_gfclk_mux",

	.flags		= HWMOD_OPT_CLKS_NEEDED,

	.prcm = {

		.omap4 = {

			.clkctrl_offs = DRA7XX_CM_L4PER2_MCASP7_CLKCTRL_OFFSET,

			.context_offs = DRA7XX_RM_L4PER2_MCASP7_CONTEXT_OFFSET,

			.modulemode   = MODULEMODE_SWCTRL,

		},

	},

	.opt_clks	= mcasp7_opt_clks,

	.opt_clks_cnt	= ARRAY_SIZE(mcasp7_opt_clks),

};



/* mcasp8 */

static struct omap_hwmod_opt_clk mcasp8_opt_clks[] = {

	{ .role = "ahclkx", .clk = "mcasp8_ahclkx_mux" },

};



static struct omap_hwmod dra7xx_mcasp8_hwmod = {

	.name		= "mcasp8",

	.class		= &dra7xx_mcasp_hwmod_class,

	.clkdm_name	= "l4per2_clkdm",

	.main_clk	= "mcasp8_aux_gfclk_mux",

	.flags		= HWMOD_OPT_CLKS_NEEDED,

	.prcm = {

		.omap4 = {

			.clkctrl_offs = DRA7XX_CM_L4PER2_MCASP8_CLKCTRL_OFFSET,

			.context_offs = DRA7XX_RM_L4PER2_MCASP8_CONTEXT_OFFSET,

			.modulemode   = MODULEMODE_SWCTRL,

		},

	},

	.opt_clks	= mcasp8_opt_clks,

	.opt_clks_cnt	= ARRAY_SIZE(mcasp8_opt_clks),

};



/*

 * 'mmc' class

 *
@@ -1707,6 +1925,8 @@ static struct omap_hwmod_class_sysconfig dra7xx_rtcss_sysc = { 
static struct omap_hwmod_class dra7xx_rtcss_hwmod_class = {

	.name	= "rtcss",

	.sysc	= &dra7xx_rtcss_sysc,

	.unlock	= &omap_hwmod_rtc_unlock,

	.lock	= &omap_hwmod_rtc_lock,

};



/* rtcss */
@@ -2065,6 +2285,20 @@ static struct omap_hwmod dra7xx_timer11_hwmod = { 
	},

};



/* timer12 */

static struct omap_hwmod dra7xx_timer12_hwmod = {

	.name		= "timer12",

	.class		= &dra7xx_timer_hwmod_class,

	.clkdm_name	= "wkupaon_clkdm",

	.main_clk	= "secure_32k_clk_src_ck",

	.prcm = {

		.omap4 = {

			.clkctrl_offs = DRA7XX_CM_WKUPAON_TIMER12_CLKCTRL_OFFSET,

			.context_offs = DRA7XX_RM_WKUPAON_TIMER12_CONTEXT_OFFSET,

		},

	},

};



/* timer13 */

static struct omap_hwmod dra7xx_timer13_hwmod = {

	.name		= "timer13",
@@ -2726,6 +2960,38 @@ static struct omap_hwmod_ocp_if dra7xx_l3_main_1__hdmi = { 
	.user		= OCP_USER_MPU | OCP_USER_SDMA,

};



/* l4_per2 -> mcasp1 */

static struct omap_hwmod_ocp_if dra7xx_l4_per2__mcasp1 = {

	.master		= &dra7xx_l4_per2_hwmod,

	.slave		= &dra7xx_mcasp1_hwmod,

	.clk		= "l4_root_clk_div",

	.user		= OCP_USER_MPU | OCP_USER_SDMA,

};



/* l3_main_1 -> mcasp1 */

static struct omap_hwmod_ocp_if dra7xx_l3_main_1__mcasp1 = {

	.master		= &dra7xx_l3_main_1_hwmod,

	.slave		= &dra7xx_mcasp1_hwmod,

	.clk		= "l3_iclk_div",

	.user		= OCP_USER_MPU | OCP_USER_SDMA,

};



/* l4_per2 -> mcasp2 */

static struct omap_hwmod_ocp_if dra7xx_l4_per2__mcasp2 = {

	.master		= &dra7xx_l4_per2_hwmod,

	.slave		= &dra7xx_mcasp2_hwmod,

	.clk		= "l4_root_clk_div",

	.user		= OCP_USER_MPU | OCP_USER_SDMA,

};



/* l3_main_1 -> mcasp2 */

static struct omap_hwmod_ocp_if dra7xx_l3_main_1__mcasp2 = {

	.master		= &dra7xx_l3_main_1_hwmod,

	.slave		= &dra7xx_mcasp2_hwmod,

	.clk		= "l3_iclk_div",

	.user		= OCP_USER_MPU | OCP_USER_SDMA,

};



/* l4_per2 -> mcasp3 */

static struct omap_hwmod_ocp_if dra7xx_l4_per2__mcasp3 = {

	.master		= &dra7xx_l4_per2_hwmod,
@@ -2742,6 +3008,46 @@ static struct omap_hwmod_ocp_if dra7xx_l3_main_1__mcasp3 = { 
	.user		= OCP_USER_MPU | OCP_USER_SDMA,

};



/* l4_per2 -> mcasp4 */

static struct omap_hwmod_ocp_if dra7xx_l4_per2__mcasp4 = {

	.master		= &dra7xx_l4_per2_hwmod,

	.slave		= &dra7xx_mcasp4_hwmod,

	.clk		= "l4_root_clk_div",

	.user		= OCP_USER_MPU | OCP_USER_SDMA,

};



/* l4_per2 -> mcasp5 */

static struct omap_hwmod_ocp_if dra7xx_l4_per2__mcasp5 = {

	.master		= &dra7xx_l4_per2_hwmod,

	.slave		= &dra7xx_mcasp5_hwmod,

	.clk		= "l4_root_clk_div",

	.user		= OCP_USER_MPU | OCP_USER_SDMA,

};



/* l4_per2 -> mcasp6 */

static struct omap_hwmod_ocp_if dra7xx_l4_per2__mcasp6 = {

	.master		= &dra7xx_l4_per2_hwmod,

	.slave		= &dra7xx_mcasp6_hwmod,

	.clk		= "l4_root_clk_div",

	.user		= OCP_USER_MPU | OCP_USER_SDMA,

};



/* l4_per2 -> mcasp7 */

static struct omap_hwmod_ocp_if dra7xx_l4_per2__mcasp7 = {

	.master		= &dra7xx_l4_per2_hwmod,

	.slave		= &dra7xx_mcasp7_hwmod,

	.clk		= "l4_root_clk_div",

	.user		= OCP_USER_MPU | OCP_USER_SDMA,

};



/* l4_per2 -> mcasp8 */

static struct omap_hwmod_ocp_if dra7xx_l4_per2__mcasp8 = {

	.master		= &dra7xx_l4_per2_hwmod,

	.slave		= &dra7xx_mcasp8_hwmod,

	.clk		= "l4_root_clk_div",

	.user		= OCP_USER_MPU | OCP_USER_SDMA,

};



/* l4_per1 -> elm */

static struct omap_hwmod_ocp_if dra7xx_l4_per1__elm = {

	.master		= &dra7xx_l4_per1_hwmod,
@@ -3281,6 +3587,14 @@ static struct omap_hwmod_ocp_if dra7xx_l4_per1__timer11 = { 
	.user		= OCP_USER_MPU | OCP_USER_SDMA,

};



/* l4_wkup -> timer12 */

static struct omap_hwmod_ocp_if dra7xx_l4_wkup__timer12 = {

	.master		= &dra7xx_l4_wkup_hwmod,

	.slave		= &dra7xx_timer12_hwmod,

	.clk		= "wkupaon_iclk_mux",

	.user		= OCP_USER_MPU | OCP_USER_SDMA,

};



/* l4_per3 -> timer13 */

static struct omap_hwmod_ocp_if dra7xx_l4_per3__timer13 = {

	.master		= &dra7xx_l4_per3_hwmod,
@@ -3465,6 +3779,30 @@ static struct omap_hwmod_ocp_if dra7xx_l4_wkup__wd_timer2 = { 
	.user		= OCP_USER_MPU | OCP_USER_SDMA,

};



/* l4_per2 -> epwmss0 */

static struct omap_hwmod_ocp_if dra7xx_l4_per2__epwmss0 = {

	.master		= &dra7xx_l4_per2_hwmod,

	.slave		= &dra7xx_epwmss0_hwmod,

	.clk		= "l4_root_clk_div",

	.user		= OCP_USER_MPU,

};



/* l4_per2 -> epwmss1 */

static struct omap_hwmod_ocp_if dra7xx_l4_per2__epwmss1 = {

	.master		= &dra7xx_l4_per2_hwmod,

	.slave		= &dra7xx_epwmss1_hwmod,

	.clk		= "l4_root_clk_div",

	.user		= OCP_USER_MPU,

};



/* l4_per2 -> epwmss2 */

static struct omap_hwmod_ocp_if dra7xx_l4_per2__epwmss2 = {

	.master		= &dra7xx_l4_per2_hwmod,

	.slave		= &dra7xx_epwmss2_hwmod,

	.clk		= "l4_root_clk_div",

	.user		= OCP_USER_MPU,

};



static struct omap_hwmod_ocp_if *dra7xx_hwmod_ocp_ifs[] __initdata = {

	&dra7xx_l3_main_1__dmm,

	&dra7xx_l3_main_2__l3_instr,
@@ -3484,8 +3822,17 @@ static struct omap_hwmod_ocp_if *dra7xx_hwmod_ocp_ifs[] __initdata = { 
	&dra7xx_l4_wkup__dcan1,

	&dra7xx_l4_per2__dcan2,

	&dra7xx_l4_per2__cpgmac0,

	&dra7xx_l4_per2__mcasp1,

	&dra7xx_l3_main_1__mcasp1,

	&dra7xx_l4_per2__mcasp2,

	&dra7xx_l3_main_1__mcasp2,

	&dra7xx_l4_per2__mcasp3,

	&dra7xx_l3_main_1__mcasp3,

	&dra7xx_l4_per2__mcasp4,

	&dra7xx_l4_per2__mcasp5,

	&dra7xx_l4_per2__mcasp6,

	&dra7xx_l4_per2__mcasp7,

	&dra7xx_l4_per2__mcasp8,

	&dra7xx_gmac__mdio,

	&dra7xx_l4_cfg__dma_system,

	&dra7xx_l3_main_1__tpcc,
@@ -3577,9 +3924,19 @@ static struct omap_hwmod_ocp_if *dra7xx_hwmod_ocp_ifs[] __initdata = { 
	&dra7xx_l3_main_1__vcp2,

	&dra7xx_l4_per2__vcp2,

	&dra7xx_l4_wkup__wd_timer2,

	&dra7xx_l4_per2__epwmss0,

	&dra7xx_l4_per2__epwmss1,

	&dra7xx_l4_per2__epwmss2,

	NULL,

};



/* GP-only hwmod links */

static struct omap_hwmod_ocp_if *dra7xx_gp_hwmod_ocp_ifs[] __initdata = {

	&dra7xx_l4_wkup__timer12,

	NULL,

};



/* SoC variant specific hwmod links */

static struct omap_hwmod_ocp_if *dra74x_hwmod_ocp_ifs[] __initdata = {

	&dra7xx_l4_per3__usb_otg_ss4,

	NULL,
@@ -3597,9 +3954,12 @@ int __init dra7xx_hwmod_init(void) 
	ret = omap_hwmod_register_links(dra7xx_hwmod_ocp_ifs);



	if (!ret && soc_is_dra74x())

		return omap_hwmod_register_links(dra74x_hwmod_ocp_ifs);

		ret = omap_hwmod_register_links(dra74x_hwmod_ocp_ifs);

	else if (!ret && soc_is_dra72x())

		return omap_hwmod_register_links(dra72x_hwmod_ocp_ifs);

		ret = omap_hwmod_register_links(dra72x_hwmod_ocp_ifs);



	if (!ret && omap_type() == OMAP2_DEVICE_TYPE_GP)

		ret = omap_hwmod_register_links(dra7xx_gp_hwmod_ocp_ifs);



	return ret;

}

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