Commit 22251a9b authored by Arnd Bergmann's avatar Arnd Bergmann Committed by Olof Johansson
Browse files

Merge branch 'lpc32xx/dt' of git://git.antcom.de/linux-2.6 into next/dt 

Roland Stigge <stigge@antcom.de> writes:
  this is a rearrangement of all mach-lpc32xx specific patches for device
  tree conversion. Please note that:

  * It builds upon the i2c-pnx changes (see previous pull request, branch
    lpc32xx/i2c)
  * Dave Miller gave permission to merge the lpc_eth.c change via arm-soc
    (patch 1/8)

  The rest of the patches is mach-lpc32xx only.

* 'lpc32xx/dt' of git://git.antcom.de/linux-2.6

:
  ARM: LPC32xx: Defconfig update
  ARM: LPC32xx: Move common code to common.c
  ARM: LPC32xx: Device tree support
  ARM: LPC32xx: DTS files for device tree conversion
  ARM: LPC32xx: Remove obsolete platform Kconfig
  ARM: LPC32xx: clock.c registration adjustment
  ARM: LPC32xx: clock.c cleanup
  net: Add device tree support to LPC32xx

Signed-off-by: default avatarArnd Bergmann <arnd@arndb.de>
[olof: rebuilt branch due to drop of an early merge]
Signed-off-by: default avatarOlof Johansson <olof@lixom.net>
parents 48bfdb21 89982a18

Documentation/devicetree/bindings/arm/lpc32xx-mic.txt

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* NXP LPC32xx Main Interrupt Controller

  (MIC, including SIC1 and SIC2 secondary controllers)



Required properties:

- compatible: Should be "nxp,lpc3220-mic"

- interrupt-controller: Identifies the node as an interrupt controller.

- interrupt-parent: Empty for the interrupt controller itself

- #interrupt-cells: The number of cells to define the interrupts. Should be 2.

  The first cell is the IRQ number

  The second cell is used to specify mode:

      1 = low-to-high edge triggered

      2 = high-to-low edge triggered

      4 = active high level-sensitive

      8 = active low level-sensitive

      Default for internal sources should be set to 4 (active high).

- reg: Should contain MIC registers location and length



Examples:

	/*

	 * MIC

	 */

	mic: interrupt-controller@40008000 {

		compatible = "nxp,lpc3220-mic";

		interrupt-controller;

		interrupt-parent;

		#interrupt-cells = <2>;

		reg = <0x40008000 0xC000>;

	};



	/*

	 * ADC

	 */

	adc@40048000 {

		compatible = "nxp,lpc3220-adc";

		reg = <0x40048000 0x1000>;

		interrupt-parent = <&mic>;

		interrupts = <39 4>;

	};

Documentation/devicetree/bindings/arm/lpc32xx.txt

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NXP LPC32xx Platforms Device Tree Bindings

------------------------------------------



Boards with the NXP LPC32xx SoC shall have the following properties:



Required root node property:



compatible: must be "nxp,lpc3220", "nxp,lpc3230", "nxp,lpc3240" or "nxp,lpc3250"

Documentation/devicetree/bindings/net/lpc-eth.txt

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* NXP LPC32xx SoC Ethernet Controller



Required properties:

- compatible: Should be "nxp,lpc-eth"

- reg: Address and length of the register set for the device

- interrupts: Should contain ethernet controller interrupt



Optional properties:

- phy-mode: String, operation mode of the PHY interface.

  Supported values are: "mii", "rmii" (default)

- use-iram: Use LPC32xx internal SRAM (IRAM) for DMA buffering

- local-mac-address : 6 bytes, mac address



Example:



	mac: ethernet@31060000 {

		compatible = "nxp,lpc-eth";

		reg = <0x31060000 0x1000>;

		interrupt-parent = <&mic>;

		interrupts = <29 0>;



		phy-mode = "rmii";

		use-iram;

	};

arch/arm/Kconfig

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@@ -597,6 +597,7 @@ config ARCH_LPC32XX 
	select USB_ARCH_HAS_OHCI

	select CLKDEV_LOOKUP

	select GENERIC_CLOCKEVENTS

	select USE_OF

	help

	  Support for the NXP LPC32XX family of processors

arch/arm/boot/dts/lpc32xx.dtsi

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/*

 * NXP LPC32xx SoC

 *

 * Copyright 2012 Roland Stigge <stigge@antcom.de>

 *

 * The code contained herein is licensed under the GNU General Public

 * License. You may obtain a copy of the GNU General Public License

 * Version 2 or later at the following locations:

 *

 * http://www.opensource.org/licenses/gpl-license.html

 * http://www.gnu.org/copyleft/gpl.html

 */



/include/ "skeleton.dtsi"



/ {

	compatible = "nxp,lpc3220";

	interrupt-parent = <&mic>;



	cpus {

		cpu@0 {

			compatible = "arm,arm926ejs";

		};

	};



	ahb {

		#address-cells = <1>;

		#size-cells = <1>;

		compatible = "simple-bus";

		ranges = <0x20000000 0x20000000 0x30000000>;



		/*

		 * Enable either SLC or MLC

		 */

		slc: flash@20020000 {

			compatible = "nxp,lpc3220-slc";

			reg = <0x20020000 0x1000>;

			status = "disable";

		};



		mlc: flash@200B0000 {

			compatible = "nxp,lpc3220-mlc";

			reg = <0x200B0000 0x1000>;

			status = "disable";

		};



		dma@31000000 {

			compatible = "arm,pl080", "arm,primecell";

			reg = <0x31000000 0x1000>;

			interrupts = <0x1c 0>;

		};



		/*

		 * Enable either ohci or usbd (gadget)!

		 */

		ohci@31020000 {

			compatible = "nxp,ohci-nxp", "usb-ohci";

			reg = <0x31020000 0x300>;

			interrupts = <0x3b 0>;

			status = "disable";

		};



		usbd@31020000 {

			compatible = "nxp,lpc3220-udc";

			reg = <0x31020000 0x300>;

			interrupts = <0x3d 0>, <0x3e 0>, <0x3c 0>, <0x3a 0>;

			status = "disable";

		};



		clcd@31040000 {

			compatible = "arm,pl110", "arm,primecell";

			reg = <0x31040000 0x1000>;

			interrupts = <0x0e 0>;

			status = "disable";

		};



		mac: ethernet@31060000 {

			compatible = "nxp,lpc-eth";

			reg = <0x31060000 0x1000>;

			interrupts = <0x1d 0>;

		};



		apb {

			#address-cells = <1>;

			#size-cells = <1>;

			compatible = "simple-bus";

			ranges = <0x20000000 0x20000000 0x30000000>;



			ssp0: ssp@20084000 {

				compatible = "arm,pl022", "arm,primecell";

				reg = <0x20084000 0x1000>;

				interrupts = <0x14 0>;

			};



			spi1: spi@20088000 {

				compatible = "nxp,lpc3220-spi";

				reg = <0x20088000 0x1000>;

			};



			ssp1: ssp@2008c000 {

				compatible = "arm,pl022", "arm,primecell";

				reg = <0x2008c000 0x1000>;

				interrupts = <0x15 0>;

			};



			spi2: spi@20090000 {

				compatible = "nxp,lpc3220-spi";

				reg = <0x20090000 0x1000>;

			};



			i2s0: i2s@20094000 {

				compatible = "nxp,lpc3220-i2s";

				reg = <0x20094000 0x1000>;

			};



			sd@20098000 {

				compatible = "arm,pl180", "arm,primecell";

				reg = <0x20098000 0x1000>;

				interrupts = <0x0f 0>, <0x0d 0>;

			};



			i2s1: i2s@2009C000 {

				compatible = "nxp,lpc3220-i2s";

				reg = <0x2009C000 0x1000>;

			};



			uart3: serial@40080000 {

				compatible = "nxp,serial";

				reg = <0x40080000 0x1000>;

			};



			uart4: serial@40088000 {

				compatible = "nxp,serial";

				reg = <0x40088000 0x1000>;

			};



			uart5: serial@40090000 {

				compatible = "nxp,serial";

				reg = <0x40090000 0x1000>;

			};



			uart6: serial@40098000 {

				compatible = "nxp,serial";

				reg = <0x40098000 0x1000>;

			};



			i2c1: i2c@400A0000 {

				compatible = "nxp,pnx-i2c";

				reg = <0x400A0000 0x100>;

				interrupts = <0x33 0>;

				#address-cells = <1>;

				#size-cells = <0>;

				pnx,timeout = <0x64>;

			};



			i2c2: i2c@400A8000 {

				compatible = "nxp,pnx-i2c";

				reg = <0x400A8000 0x100>;

				interrupts = <0x32 0>;

				#address-cells = <1>;

				#size-cells = <0>;

				pnx,timeout = <0x64>;

			};



			i2cusb: i2c@31020300 {

				compatible = "nxp,pnx-i2c";

				reg = <0x31020300 0x100>;

				interrupts = <0x3f 0>;

				#address-cells = <1>;

				#size-cells = <0>;

				pnx,timeout = <0x64>;

			};

		};



		fab {

			#address-cells = <1>;

			#size-cells = <1>;

			compatible = "simple-bus";

			ranges = <0x20000000 0x20000000 0x30000000>;



			/*

			 * MIC Interrupt controller includes:

			 *   MIC @40008000

			 *   SIC1 @4000C000

			 *   SIC2 @40010000

			 */

			mic: interrupt-controller@40008000 {

				compatible = "nxp,lpc3220-mic";

				interrupt-controller;

				reg = <0x40008000 0xC000>;

				#interrupt-cells = <2>;

			};



			uart1: serial@40014000 {

				compatible = "nxp,serial";

				reg = <0x40014000 0x1000>;

			};



			uart2: serial@40018000 {

				compatible = "nxp,serial";

				reg = <0x40018000 0x1000>;

			};



			uart7: serial@4001C000 {

				compatible = "nxp,serial";

				reg = <0x4001C000 0x1000>;

			};



			rtc@40024000 {

				compatible = "nxp,lpc3220-rtc";

				reg = <0x40024000 0x1000>;

				interrupts = <0x34 0>;

			};



			gpio: gpio@40028000 {

				compatible = "nxp,lpc3220-gpio";

				reg = <0x40028000 0x1000>;

				/* create a private address space for enumeration */

				#address-cells = <1>;

				#size-cells = <0>;



				gpio_p0: gpio-bank@0 {

					gpio-controller;

					#gpio-cells = <2>;

					reg = <0>;

				};



				gpio_p1: gpio-bank@1 {

					gpio-controller;

					#gpio-cells = <2>;

					reg = <1>;

				};



				gpio_p2: gpio-bank@2 {

					gpio-controller;

					#gpio-cells = <2>;

					reg = <2>;

				};



				gpio_p3: gpio-bank@3 {

					gpio-controller;

					#gpio-cells = <2>;

					reg = <3>;

				};



				gpi_p3: gpio-bank@4 {

					gpio-controller;

					#gpio-cells = <2>;

					reg = <4>;

				};



				gpo_p3: gpio-bank@5 {

					gpio-controller;

					#gpio-cells = <2>;

					reg = <5>;

				};

			};



			watchdog@4003C000 {

				compatible = "nxp,pnx4008-wdt";

				reg = <0x4003C000 0x1000>;

			};



			/*

			 * TSC vs. ADC: Since those two share the same

			 * hardware, you need to choose from one of the

			 * following two and do 'status = "okay";' for one of

			 * them

			 */



			adc@40048000 {

				compatible = "nxp,lpc3220-adc";

				reg = <0x40048000 0x1000>;

				interrupts = <0x27 0>;

				status = "disable";

			};



			tsc@40048000 {

				compatible = "nxp,lpc3220-tsc";

				reg = <0x40048000 0x1000>;

				interrupts = <0x27 0>;

				status = "disable";

			};



			key@40050000 {

				compatible = "nxp,lpc3220-key";

				reg = <0x40050000 0x1000>;

			};



		};

	};

};

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