Commit 221c7862 authored by Chris Wilson's avatar Chris Wilson
Browse files

drm/i915: Lift acquiring the vlv punit magic to a common sb-get 



As we now employ a very heavy pm_qos around the punit access, we want to
minimise the number of synchronous requests by performing one for the
whole punit sequence rather than around individual accesses. The
sideband lock is used for this, so push the pm_qos into the sideband
lock acquisition and release, moving it from the lowlevel punit rw
routine to the callers. In the first step, we move the punit magic into
the common sideband lock so that we can acquire a bunch of ports
simultaneously, and if need be extend the workaround protection later.

Signed-off-by: default avatarChris Wilson <chris@chris-wilson.co.uk>
Reviewed-by: default avatarVille Syrjälä <ville.syrjala@linux.intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20190426081725.31217-2-chris@chris-wilson.co.uk
parent a75d035f

drivers/gpu/drm/i915/i915_drv.h

+109 −15
Original line number Diff line number Diff line
@@ -3442,25 +3442,119 @@ int skl_pcode_request(struct drm_i915_private *dev_priv, u32 mbox, u32 request, 
		      u32 reply_mask, u32 reply, int timeout_base_ms);



/* intel_sideband.c */

u32 vlv_punit_read(struct drm_i915_private *dev_priv, u32 addr);

int vlv_punit_write(struct drm_i915_private *dev_priv, u32 addr, u32 val);

u32 vlv_nc_read(struct drm_i915_private *dev_priv, u8 addr);

u32 vlv_iosf_sb_read(struct drm_i915_private *dev_priv, u8 port, u32 reg);

void vlv_iosf_sb_write(struct drm_i915_private *dev_priv, u8 port, u32 reg, u32 val);

u32 vlv_cck_read(struct drm_i915_private *dev_priv, u32 reg);

void vlv_cck_write(struct drm_i915_private *dev_priv, u32 reg, u32 val);

u32 vlv_ccu_read(struct drm_i915_private *dev_priv, u32 reg);

void vlv_ccu_write(struct drm_i915_private *dev_priv, u32 reg, u32 val);

u32 vlv_bunit_read(struct drm_i915_private *dev_priv, u32 reg);

void vlv_bunit_write(struct drm_i915_private *dev_priv, u32 reg, u32 val);

u32 vlv_dpio_read(struct drm_i915_private *dev_priv, enum pipe pipe, int reg);

void vlv_dpio_write(struct drm_i915_private *dev_priv, enum pipe pipe, int reg, u32 val);



enum {

	VLV_IOSF_SB_BUNIT,

	VLV_IOSF_SB_CCK,

	VLV_IOSF_SB_CCU,

	VLV_IOSF_SB_DPIO,

	VLV_IOSF_SB_FLISDSI,

	VLV_IOSF_SB_GPIO,

	VLV_IOSF_SB_NC,

	VLV_IOSF_SB_PUNIT,

};



void vlv_iosf_sb_get(struct drm_i915_private *i915, unsigned long ports);

u32 vlv_iosf_sb_read(struct drm_i915_private *i915, u8 port, u32 reg);

void vlv_iosf_sb_write(struct drm_i915_private *i915,

		       u8 port, u32 reg, u32 val);

void vlv_iosf_sb_put(struct drm_i915_private *i915, unsigned long ports);



static inline void vlv_bunit_get(struct drm_i915_private *i915)

{

	vlv_iosf_sb_get(i915, BIT(VLV_IOSF_SB_BUNIT));

}



u32 vlv_bunit_read(struct drm_i915_private *i915, u32 reg);

void vlv_bunit_write(struct drm_i915_private *i915, u32 reg, u32 val);



static inline void vlv_bunit_put(struct drm_i915_private *i915)

{

	vlv_iosf_sb_put(i915, BIT(VLV_IOSF_SB_BUNIT));

}



static inline void vlv_cck_get(struct drm_i915_private *i915)

{

	vlv_iosf_sb_get(i915, BIT(VLV_IOSF_SB_CCK));

}



u32 vlv_cck_read(struct drm_i915_private *i915, u32 reg);

void vlv_cck_write(struct drm_i915_private *i915, u32 reg, u32 val);



static inline void vlv_cck_put(struct drm_i915_private *i915)

{

	vlv_iosf_sb_put(i915, BIT(VLV_IOSF_SB_CCK));

}



static inline void vlv_ccu_get(struct drm_i915_private *i915)

{

	vlv_iosf_sb_get(i915, BIT(VLV_IOSF_SB_CCU));

}



u32 vlv_ccu_read(struct drm_i915_private *i915, u32 reg);

void vlv_ccu_write(struct drm_i915_private *i915, u32 reg, u32 val);



static inline void vlv_ccu_put(struct drm_i915_private *i915)

{

	vlv_iosf_sb_put(i915, BIT(VLV_IOSF_SB_CCU));

}



static inline void vlv_dpio_get(struct drm_i915_private *i915)

{

	vlv_iosf_sb_get(i915, BIT(VLV_IOSF_SB_DPIO));

}



u32 vlv_dpio_read(struct drm_i915_private *i915, enum pipe pipe, int reg);

void vlv_dpio_write(struct drm_i915_private *i915,

		    enum pipe pipe, int reg, u32 val);



static inline void vlv_dpio_put(struct drm_i915_private *i915)

{

	vlv_iosf_sb_put(i915, BIT(VLV_IOSF_SB_DPIO));

}



static inline void vlv_flisdsi_get(struct drm_i915_private *i915)

{

	vlv_iosf_sb_get(i915, BIT(VLV_IOSF_SB_FLISDSI));

}



u32 vlv_flisdsi_read(struct drm_i915_private *i915, u32 reg);

void vlv_flisdsi_write(struct drm_i915_private *i915, u32 reg, u32 val);



static inline void vlv_flisdsi_put(struct drm_i915_private *i915)

{

	vlv_iosf_sb_put(i915, BIT(VLV_IOSF_SB_FLISDSI));

}



static inline void vlv_nc_get(struct drm_i915_private *i915)

{

	vlv_iosf_sb_get(i915, BIT(VLV_IOSF_SB_NC));

}



u32 vlv_nc_read(struct drm_i915_private *i915, u8 addr);



static inline void vlv_nc_put(struct drm_i915_private *i915)

{

	vlv_iosf_sb_put(i915, BIT(VLV_IOSF_SB_NC));

}



static inline void vlv_punit_get(struct drm_i915_private *i915)

{

	vlv_iosf_sb_get(i915, BIT(VLV_IOSF_SB_PUNIT));

}



u32 vlv_punit_read(struct drm_i915_private *i915, u32 addr);

int vlv_punit_write(struct drm_i915_private *i915, u32 addr, u32 val);



static inline void vlv_punit_put(struct drm_i915_private *i915)

{

	vlv_iosf_sb_put(i915, BIT(VLV_IOSF_SB_PUNIT));

}



u32 intel_sbi_read(struct drm_i915_private *dev_priv, u16 reg,

		   enum intel_sbi_destination destination);

void intel_sbi_write(struct drm_i915_private *dev_priv, u16 reg, u32 value,

		     enum intel_sbi_destination destination);

u32 vlv_flisdsi_read(struct drm_i915_private *dev_priv, u32 reg);

void vlv_flisdsi_write(struct drm_i915_private *dev_priv, u32 reg, u32 val);



/* intel_dpio_phy.c */

void bxt_port_to_phy_channel(struct drm_i915_private *dev_priv, enum port port,

drivers/gpu/drm/i915/intel_cdclk.c

+4 −2
Original line number Diff line number Diff line
@@ -557,7 +557,8 @@ static void vlv_set_cdclk(struct drm_i915_private *dev_priv, 
	}

	mutex_unlock(&dev_priv->pcu_lock);



	mutex_lock(&dev_priv->sb_lock);

	vlv_iosf_sb_get(dev_priv,

			BIT(VLV_IOSF_SB_CCK) | BIT(VLV_IOSF_SB_BUNIT));



	if (cdclk == 400000) {

		u32 divider;
@@ -591,7 +592,8 @@ static void vlv_set_cdclk(struct drm_i915_private *dev_priv, 
		val |= 3000 / 250; /* 3.0 usec */

	vlv_bunit_write(dev_priv, BUNIT_REG_BISOC, val);



	mutex_unlock(&dev_priv->sb_lock);

	vlv_iosf_sb_put(dev_priv,

			BIT(VLV_IOSF_SB_CCK) | BIT(VLV_IOSF_SB_BUNIT));



	intel_update_cdclk(dev_priv);

drivers/gpu/drm/i915/intel_display.c

+19 −18
Original line number Diff line number Diff line
@@ -152,10 +152,10 @@ int vlv_get_hpll_vco(struct drm_i915_private *dev_priv) 
	int hpll_freq, vco_freq[] = { 800, 1600, 2000, 2400 };



	/* Obtain SKU information */

	mutex_lock(&dev_priv->sb_lock);

	vlv_cck_get(dev_priv);

	hpll_freq = vlv_cck_read(dev_priv, CCK_FUSE_REG) &

		CCK_FUSE_HPLL_FREQ_MASK;

	mutex_unlock(&dev_priv->sb_lock);

	vlv_cck_put(dev_priv);



	return vco_freq[hpll_freq] * 1000;

}
@@ -166,9 +166,9 @@ int vlv_get_cck_clock(struct drm_i915_private *dev_priv, 
	u32 val;

	int divider;



	mutex_lock(&dev_priv->sb_lock);

	vlv_cck_get(dev_priv);

	val = vlv_cck_read(dev_priv, reg);

	mutex_unlock(&dev_priv->sb_lock);

	vlv_cck_put(dev_priv);



	divider = val & CCK_FREQUENCY_VALUES;
@@ -1093,9 +1093,9 @@ void assert_dsi_pll(struct drm_i915_private *dev_priv, bool state) 
	u32 val;

	bool cur_state;



	mutex_lock(&dev_priv->sb_lock);

	vlv_cck_get(dev_priv);

	val = vlv_cck_read(dev_priv, CCK_REG_DSI_PLL_CONTROL);

	mutex_unlock(&dev_priv->sb_lock);

	vlv_cck_put(dev_priv);



	cur_state = val & DSI_PLL_VCO_EN;

	I915_STATE_WARN(cur_state != state,
@@ -1405,14 +1405,14 @@ static void _chv_enable_pll(struct intel_crtc *crtc, 
	enum dpio_channel port = vlv_pipe_to_channel(pipe);

	u32 tmp;



	mutex_lock(&dev_priv->sb_lock);

	vlv_dpio_get(dev_priv);



	/* Enable back the 10bit clock to display controller */

	tmp = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW14(port));

	tmp |= DPIO_DCLKP_EN;

	vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW14(port), tmp);



	mutex_unlock(&dev_priv->sb_lock);

	vlv_dpio_put(dev_priv);



	/*

	 * Need to wait > 100ns between dclkp clock enable bit and PLL enable.
@@ -1569,14 +1569,14 @@ static void chv_disable_pll(struct drm_i915_private *dev_priv, enum pipe pipe) 
	I915_WRITE(DPLL(pipe), val);

	POSTING_READ(DPLL(pipe));



	mutex_lock(&dev_priv->sb_lock);

	vlv_dpio_get(dev_priv);



	/* Disable 10bit clock to display controller */

	val = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW14(port));

	val &= ~DPIO_DCLKP_EN;

	vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW14(port), val);



	mutex_unlock(&dev_priv->sb_lock);

	vlv_dpio_put(dev_priv);

}



void vlv_wait_port_ready(struct drm_i915_private *dev_priv,
@@ -7276,7 +7276,7 @@ static void vlv_prepare_pll(struct intel_crtc *crtc, 
	if ((pipe_config->dpll_hw_state.dpll & DPLL_VCO_ENABLE) == 0)

		return;



	mutex_lock(&dev_priv->sb_lock);

	vlv_dpio_get(dev_priv);



	bestn = pipe_config->dpll.n;

	bestm1 = pipe_config->dpll.m1;
@@ -7353,7 +7353,8 @@ static void vlv_prepare_pll(struct intel_crtc *crtc, 
	vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW7(pipe), coreclk);



	vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW11(pipe), 0x87871000);

	mutex_unlock(&dev_priv->sb_lock);



	vlv_dpio_put(dev_priv);

}



static void chv_prepare_pll(struct intel_crtc *crtc,
@@ -7386,7 +7387,7 @@ static void chv_prepare_pll(struct intel_crtc *crtc, 
	dpio_val = 0;

	loopfilter = 0;



	mutex_lock(&dev_priv->sb_lock);

	vlv_dpio_get(dev_priv);



	/* p1 and p2 divider */

	vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW13(port),
@@ -7458,7 +7459,7 @@ static void chv_prepare_pll(struct intel_crtc *crtc, 
			vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW14(port)) |

			DPIO_AFC_RECAL);



	mutex_unlock(&dev_priv->sb_lock);

	vlv_dpio_put(dev_priv);

}



/**
@@ -8084,9 +8085,9 @@ static void vlv_crtc_clock_get(struct intel_crtc *crtc, 
	if ((pipe_config->dpll_hw_state.dpll & DPLL_VCO_ENABLE) == 0)

		return;



	mutex_lock(&dev_priv->sb_lock);

	vlv_dpio_get(dev_priv);

	mdiv = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW3(pipe));

	mutex_unlock(&dev_priv->sb_lock);

	vlv_dpio_put(dev_priv);



	clock.m1 = (mdiv >> DPIO_M1DIV_SHIFT) & 7;

	clock.m2 = mdiv & DPIO_M2DIV_MASK;
@@ -8195,13 +8196,13 @@ static void chv_crtc_clock_get(struct intel_crtc *crtc, 
	if ((pipe_config->dpll_hw_state.dpll & DPLL_VCO_ENABLE) == 0)

		return;



	mutex_lock(&dev_priv->sb_lock);

	vlv_dpio_get(dev_priv);

	cmn_dw13 = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW13(port));

	pll_dw0 = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW0(port));

	pll_dw1 = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW1(port));

	pll_dw2 = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW2(port));

	pll_dw3 = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW3(port));

	mutex_unlock(&dev_priv->sb_lock);

	vlv_dpio_put(dev_priv);



	clock.m1 = (pll_dw1 & 0x7) == DPIO_CHV_M1_DIV_BY_2 ? 2 : 0;

	clock.m2 = (pll_dw0 & 0xff) << 22;

drivers/gpu/drm/i915/intel_dp.c

+2 −2
Original line number Diff line number Diff line
@@ -3148,12 +3148,12 @@ static void chv_post_disable_dp(struct intel_encoder *encoder, 


	intel_dp_link_down(encoder, old_crtc_state);



	mutex_lock(&dev_priv->sb_lock);

	vlv_dpio_get(dev_priv);



	/* Assert data lane reset */

	chv_data_lane_soft_reset(encoder, old_crtc_state, true);



	mutex_unlock(&dev_priv->sb_lock);

	vlv_dpio_put(dev_priv);

}



static void

drivers/gpu/drm/i915/intel_dpio_phy.c

+20 −17
Original line number Diff line number Diff line
@@ -648,7 +648,7 @@ void chv_set_phy_signal_level(struct intel_encoder *encoder, 
	u32 val;

	int i;



	mutex_lock(&dev_priv->sb_lock);

	vlv_dpio_get(dev_priv);



	/* Clear calc init */

	val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW10(ch));
@@ -729,8 +729,7 @@ void chv_set_phy_signal_level(struct intel_encoder *encoder, 
		vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW10(ch), val);

	}



	mutex_unlock(&dev_priv->sb_lock);



	vlv_dpio_put(dev_priv);

}



void chv_data_lane_soft_reset(struct intel_encoder *encoder,
@@ -800,7 +799,7 @@ void chv_phy_pre_pll_enable(struct intel_encoder *encoder, 


	chv_phy_powergate_lanes(encoder, true, lane_mask);



	mutex_lock(&dev_priv->sb_lock);

	vlv_dpio_get(dev_priv);



	/* Assert data lane reset */

	chv_data_lane_soft_reset(encoder, crtc_state, true);
@@ -855,7 +854,7 @@ void chv_phy_pre_pll_enable(struct intel_encoder *encoder, 
		val |= CHV_CMN_USEDCLKCHANNEL;

	vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW19(ch), val);



	mutex_unlock(&dev_priv->sb_lock);

	vlv_dpio_put(dev_priv);

}



void chv_phy_pre_encoder_enable(struct intel_encoder *encoder,
@@ -870,7 +869,7 @@ void chv_phy_pre_encoder_enable(struct intel_encoder *encoder, 
	int data, i, stagger;

	u32 val;



	mutex_lock(&dev_priv->sb_lock);

	vlv_dpio_get(dev_priv);



	/* allow hardware to manage TX FIFO reset source */

	val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW11(ch));
@@ -935,7 +934,7 @@ void chv_phy_pre_encoder_enable(struct intel_encoder *encoder, 
	/* Deassert data lane reset */

	chv_data_lane_soft_reset(encoder, crtc_state, false);



	mutex_unlock(&dev_priv->sb_lock);

	vlv_dpio_put(dev_priv);

}



void chv_phy_release_cl2_override(struct intel_encoder *encoder)
@@ -956,7 +955,7 @@ void chv_phy_post_pll_disable(struct intel_encoder *encoder, 
	enum pipe pipe = to_intel_crtc(old_crtc_state->base.crtc)->pipe;

	u32 val;



	mutex_lock(&dev_priv->sb_lock);

	vlv_dpio_get(dev_priv);



	/* disable left/right clock distribution */

	if (pipe != PIPE_B) {
@@ -969,7 +968,7 @@ void chv_phy_post_pll_disable(struct intel_encoder *encoder, 
		vlv_dpio_write(dev_priv, pipe, _CHV_CMN_DW1_CH1, val);

	}



	mutex_unlock(&dev_priv->sb_lock);

	vlv_dpio_put(dev_priv);



	/*

	 * Leave the power down bit cleared for at least one
@@ -993,7 +992,8 @@ void vlv_set_phy_signal_level(struct intel_encoder *encoder, 
	enum dpio_channel port = vlv_dport_to_channel(dport);

	enum pipe pipe = intel_crtc->pipe;



	mutex_lock(&dev_priv->sb_lock);

	vlv_dpio_get(dev_priv);



	vlv_dpio_write(dev_priv, pipe, VLV_TX_DW5(port), 0x00000000);

	vlv_dpio_write(dev_priv, pipe, VLV_TX_DW4(port), demph_reg_value);

	vlv_dpio_write(dev_priv, pipe, VLV_TX_DW2(port),
@@ -1006,7 +1006,8 @@ void vlv_set_phy_signal_level(struct intel_encoder *encoder, 
	vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW11(port), 0x00030000);

	vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW9(port), preemph_reg_value);

	vlv_dpio_write(dev_priv, pipe, VLV_TX_DW5(port), DPIO_TX_OCALINIT_EN);

	mutex_unlock(&dev_priv->sb_lock);



	vlv_dpio_put(dev_priv);

}



void vlv_phy_pre_pll_enable(struct intel_encoder *encoder,
@@ -1019,7 +1020,8 @@ void vlv_phy_pre_pll_enable(struct intel_encoder *encoder, 
	enum pipe pipe = crtc->pipe;



	/* Program Tx lane resets to default */

	mutex_lock(&dev_priv->sb_lock);

	vlv_dpio_get(dev_priv);



	vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW0(port),

			 DPIO_PCS_TX_LANE2_RESET |

			 DPIO_PCS_TX_LANE1_RESET);
@@ -1033,7 +1035,8 @@ void vlv_phy_pre_pll_enable(struct intel_encoder *encoder, 
	vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW12(port), 0x00750f00);

	vlv_dpio_write(dev_priv, pipe, VLV_TX_DW11(port), 0x00001500);

	vlv_dpio_write(dev_priv, pipe, VLV_TX_DW14(port), 0x40400000);

	mutex_unlock(&dev_priv->sb_lock);



	vlv_dpio_put(dev_priv);

}



void vlv_phy_pre_encoder_enable(struct intel_encoder *encoder,
@@ -1047,7 +1050,7 @@ void vlv_phy_pre_encoder_enable(struct intel_encoder *encoder, 
	enum pipe pipe = crtc->pipe;

	u32 val;



	mutex_lock(&dev_priv->sb_lock);

	vlv_dpio_get(dev_priv);



	/* Enable clock channels for this port */

	val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW8(port));
@@ -1063,7 +1066,7 @@ void vlv_phy_pre_encoder_enable(struct intel_encoder *encoder, 
	vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW14(port), 0x00760018);

	vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW23(port), 0x00400888);



	mutex_unlock(&dev_priv->sb_lock);

	vlv_dpio_put(dev_priv);

}



void vlv_phy_reset_lanes(struct intel_encoder *encoder,
@@ -1075,8 +1078,8 @@ void vlv_phy_reset_lanes(struct intel_encoder *encoder, 
	enum dpio_channel port = vlv_dport_to_channel(dport);

	enum pipe pipe = crtc->pipe;



	mutex_lock(&dev_priv->sb_lock);

	vlv_dpio_get(dev_priv);

	vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW0(port), 0x00000000);

	vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW1(port), 0x00e00060);

	mutex_unlock(&dev_priv->sb_lock);

	vlv_dpio_put(dev_priv);

}

CRA Git | Maintained and supported by SUSTech CRA and CCSE