Commit 21eb9ec7 authored by Long Cheng's avatar Long Cheng Committed by Matthias Brugger
Browse files

arm: dts: mt2712: add uart APDMA to device tree 



1. add uart APDMA controller device node
2. add uart 0/1/2/3/4/5 DMA function

Signed-off-by: default avatarLong Cheng <long.cheng@mediatek.com>
Link: https://lore.kernel.org/r/1556336193-15198-3-git-send-email-long.cheng@mediatek.com


Signed-off-by: default avatarMatthias Brugger <matthias.bgg@gmail.com>
parent 5e6cdf00

arch/arm64/boot/dts/mediatek/mt2712e.dtsi

+51 −0
Original line number Diff line number Diff line
@@ -300,6 +300,9 @@ 
		interrupts = <GIC_SPI 127 IRQ_TYPE_LEVEL_LOW>;

		clocks = <&baud_clk>, <&sys_clk>;

		clock-names = "baud", "bus";

		dmas = <&apdma 10

			&apdma 11>;

		dma-names = "tx", "rx";

		status = "disabled";

	};
@@ -375,6 +378,39 @@ 
			 (GIC_CPU_MASK_RAW(0x13) | IRQ_TYPE_LEVEL_HIGH)>;

	};



	apdma: dma-controller@11000400 {

		compatible = "mediatek,mt2712-uart-dma",

			     "mediatek,mt6577-uart-dma";

		reg = <0 0x11000400 0 0x80>,

		      <0 0x11000480 0 0x80>,

		      <0 0x11000500 0 0x80>,

		      <0 0x11000580 0 0x80>,

		      <0 0x11000600 0 0x80>,

		      <0 0x11000680 0 0x80>,

		      <0 0x11000700 0 0x80>,

		      <0 0x11000780 0 0x80>,

		      <0 0x11000800 0 0x80>,

		      <0 0x11000880 0 0x80>,

		      <0 0x11000900 0 0x80>,

		      <0 0x11000980 0 0x80>;

		interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_LOW>,

			     <GIC_SPI 104 IRQ_TYPE_LEVEL_LOW>,

			     <GIC_SPI 105 IRQ_TYPE_LEVEL_LOW>,

			     <GIC_SPI 106 IRQ_TYPE_LEVEL_LOW>,

			     <GIC_SPI 107 IRQ_TYPE_LEVEL_LOW>,

			     <GIC_SPI 108 IRQ_TYPE_LEVEL_LOW>,

			     <GIC_SPI 109 IRQ_TYPE_LEVEL_LOW>,

			     <GIC_SPI 110 IRQ_TYPE_LEVEL_LOW>,

			     <GIC_SPI 111 IRQ_TYPE_LEVEL_LOW>,

			     <GIC_SPI 112 IRQ_TYPE_LEVEL_LOW>,

			     <GIC_SPI 113 IRQ_TYPE_LEVEL_LOW>,

			     <GIC_SPI 114 IRQ_TYPE_LEVEL_LOW>;

		dma-requests = <12>;

		clocks = <&pericfg CLK_PERI_AP_DMA>;

		clock-names = "apdma";

		#dma-cells = <1>;

	};



	auxadc: adc@11001000 {

		compatible = "mediatek,mt2712-auxadc";

		reg = <0 0x11001000 0 0x1000>;
@@ -391,6 +427,9 @@ 
		interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_LOW>;

		clocks = <&baud_clk>, <&sys_clk>;

		clock-names = "baud", "bus";

		dmas = <&apdma 0

			&apdma 1>;

		dma-names = "tx", "rx";

		status = "disabled";

	};
@@ -401,6 +440,9 @@ 
		interrupts = <GIC_SPI 92 IRQ_TYPE_LEVEL_LOW>;

		clocks = <&baud_clk>, <&sys_clk>;

		clock-names = "baud", "bus";

		dmas = <&apdma 2

			&apdma 3>;

		dma-names = "tx", "rx";

		status = "disabled";

	};
@@ -411,6 +453,9 @@ 
		interrupts = <GIC_SPI 93 IRQ_TYPE_LEVEL_LOW>;

		clocks = <&baud_clk>, <&sys_clk>;

		clock-names = "baud", "bus";

		dmas = <&apdma 4

			&apdma 5>;

		dma-names = "tx", "rx";

		status = "disabled";

	};
@@ -421,6 +466,9 @@ 
		interrupts = <GIC_SPI 94 IRQ_TYPE_LEVEL_LOW>;

		clocks = <&baud_clk>, <&sys_clk>;

		clock-names = "baud", "bus";

		dmas = <&apdma 6

			&apdma 7>;

		dma-names = "tx", "rx";

		status = "disabled";

	};
@@ -635,6 +683,9 @@ 
		interrupts = <GIC_SPI 126 IRQ_TYPE_LEVEL_LOW>;

		clocks = <&baud_clk>, <&sys_clk>;

		clock-names = "baud", "bus";

		dmas = <&apdma 8

			&apdma 9>;

		dma-names = "tx", "rx";

		status = "disabled";

	};

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