Commit 21e6bff5 authored Mar 07, 2019 by Nicholas Piggin Committed by Ley Foon Tan Mar 07, 2019

nios2: Fix update_mmu_cache preload the TLB with the new PTE



There is a bug in the TLB preload caused by the pid not being
shifted to the correct location in tlbmisc register.

Signed-off-by: Nicholas Piggin <npiggin@gmail.com>
Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com>
Tested-by: Guenter Roeck <linux@roeck-us.net>

parent 3ac23944

arch/nios2/mm/tlb.c

+2 −1

Original line number	Diff line number	Diff line
		@@ -70,7 +70,8 @@ static void replace_tlb_one_pid(unsigned long addr, unsigned long mmu_pid, unsig
		if (pid != mmu_pid)
		continue;

		tlbmisc = mmu_pid \| TLBMISC_WE \| (way << TLBMISC_WAY_SHIFT);
		tlbmisc = (mmu_pid << TLBMISC_PID_SHIFT) \| TLBMISC_WE \|
		(way << TLBMISC_WAY_SHIFT);
		WRCTL(CTL_TLBMISC, tlbmisc);
		if (tlbacc == 0)
		WRCTL(CTL_PTEADDR, pteaddr_invalid(addr));

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