Commit 21c5b3c6 authored by Linus Torvalds's avatar Linus Torvalds
Browse files

Merge tag 'drm-next-2020-04-10' of git://anongit.freedesktop.org/drm/drm 

Pull more drm fixes from Dave Airlie:
 "As expected, more fixes did turn up in the latter part of the week.

  The drm_local_map build regression fix is here, along with temporary
  disabling of the hugepage work due to some amdgpu related crashes.

  Otherwise it's just a bunch of i915, and amdgpu fixes.

  legacy:
   - fix drm_local_map.offset type

  ttm:
   - temporarily disable hugepages to debug amdgpu problems.

  prime:
   - fix sg extraction

  amdgpu:
   - Various Renoir fixes
   - Fix gfx clockgating sequence on gfx10
   - RAS fixes
   - Avoid MST property creation after registration
   - Various cursor/viewport fixes
   - Fix a confusing log message about optional firmwares

  i915:
   - Flush all the reloc_gpu batch (Chris)
   - Ignore readonly failures when updating relocs (Chris)
   - Fill all the unused space in the GGTT (Chris)
   - Return the right vswing table (Jose)
   - Don't enable DDI IO power on a TypeC port in TBT mode for ICL+ (Imre)

  analogix_dp:
   - probe fix

  virtio:
   - oob fix in object create"

* tag 'drm-next-2020-04-10' of git://anongit.freedesktop.org/drm/drm: (34 commits)
  drm/ttm: Temporarily disable the huge_fault() callback
  drm/bridge: analogix_dp: Split bind() into probe() and real bind()
  drm/legacy: Fix type for drm_local_map.offset
  drm/amdgpu/display: fix warning when compiling without debugfs
  drm/amdgpu: unify fw_write_wait for new gfx9 asics
  drm/amd/powerplay: error out on forcing clock setting not supported
  drm/amdgpu: fix gfx hang during suspend with video playback (v2)
  drm/amd/display: Check for null fclk voltage when parsing clock table
  drm/amd/display: Acknowledge wm_optimized_required
  drm/amd/display: Make cursor source translation adjustment optional
  drm/amd/display: Calculate scaling ratios on every medium/full update
  drm/amd/display: Program viewport when source pos changes for DCN20 hw seq
  drm/amd/display: Fix incorrect cursor pos on scaled primary plane
  drm/amd/display: change default pipe_split policy for DCN1
  drm/amd/display: Translate cursor position by source rect
  drm/amd/display: Update stream adjust in dc_stream_adjust_vmin_vmax
  drm/amd/display: Avoid create MST prop after registration
  drm/amdgpu/psp: dont warn on missing optional TA's
  drm/amdgpu: update RAS related dmesg print
  drm/amdgpu: resolve mGPU RAS query instability
  ...
parents 4aafdf68 74bd4f0c

drivers/gpu/drm/amd/amdgpu/amdgpu_device.c

+3 −2
Original line number Diff line number Diff line
@@ -2340,8 +2340,6 @@ static int amdgpu_device_ip_suspend_phase1(struct amdgpu_device *adev) 
{

	int i, r;



	amdgpu_device_set_pg_state(adev, AMD_PG_STATE_UNGATE);

	amdgpu_device_set_cg_state(adev, AMD_CG_STATE_UNGATE);



	for (i = adev->num_ip_blocks - 1; i >= 0; i--) {

		if (!adev->ip_blocks[i].status.valid)
@@ -3356,6 +3354,9 @@ int amdgpu_device_suspend(struct drm_device *dev, bool fbcon) 
		}

	}



	amdgpu_device_set_pg_state(adev, AMD_PG_STATE_UNGATE);

	amdgpu_device_set_cg_state(adev, AMD_CG_STATE_UNGATE);



	amdgpu_amdkfd_suspend(adev, !fbcon);



	amdgpu_ras_suspend(adev);

drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c

+2 −1
Original line number Diff line number Diff line
@@ -89,7 +89,8 @@ void amdgpu_pm_acpi_event_handler(struct amdgpu_device *adev) 
			adev->pm.ac_power = true;

		else

			adev->pm.ac_power = false;

		if (adev->powerplay.pp_funcs->enable_bapm)

		if (adev->powerplay.pp_funcs &&

		    adev->powerplay.pp_funcs->enable_bapm)

			amdgpu_dpm_enable_bapm(adev, adev->pm.ac_power);

		mutex_unlock(&adev->pm.mutex);

drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c

+3 −3
Original line number Diff line number Diff line
@@ -818,7 +818,7 @@ static int psp_ras_initialize(struct psp_context *psp) 


	if (!psp->adev->psp.ta_ras_ucode_size ||

	    !psp->adev->psp.ta_ras_start_addr) {

		dev_warn(psp->adev->dev, "RAS: ras ta ucode is not available\n");

		dev_info(psp->adev->dev, "RAS: optional ras ta ucode is not available\n");

		return 0;

	}
@@ -902,7 +902,7 @@ static int psp_hdcp_initialize(struct psp_context *psp) 


	if (!psp->adev->psp.ta_hdcp_ucode_size ||

	    !psp->adev->psp.ta_hdcp_start_addr) {

		dev_warn(psp->adev->dev, "HDCP: hdcp ta ucode is not available\n");

		dev_info(psp->adev->dev, "HDCP: optional hdcp ta ucode is not available\n");

		return 0;

	}
@@ -1048,7 +1048,7 @@ static int psp_dtm_initialize(struct psp_context *psp) 


	if (!psp->adev->psp.ta_dtm_ucode_size ||

	    !psp->adev->psp.ta_dtm_start_addr) {

		dev_warn(psp->adev->dev, "DTM: dtm ta ucode is not available\n");

		dev_info(psp->adev->dev, "DTM: optional dtm ta ucode is not available\n");

		return 0;

	}

drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c

+15 −5
Original line number Diff line number Diff line
@@ -1424,12 +1424,22 @@ static void amdgpu_ras_do_recovery(struct work_struct *work) 
{

	struct amdgpu_ras *ras =

		container_of(work, struct amdgpu_ras, recovery_work);

	struct amdgpu_device *remote_adev = NULL;

	struct amdgpu_device *adev = ras->adev;

	struct list_head device_list, *device_list_handle =  NULL;

	struct amdgpu_hive_info *hive = amdgpu_get_xgmi_hive(adev, false);



	/* Build list of devices to query RAS related errors */

	if  (hive && adev->gmc.xgmi.num_physical_nodes > 1) {

		device_list_handle = &hive->device_list;

	} else {

		list_add_tail(&adev->gmc.xgmi.head, &device_list);

		device_list_handle = &device_list;

	}



	/*

	 * Query and print non zero error counter per IP block for

	 * awareness before recovering GPU.

	 */

	amdgpu_ras_log_on_err_counter(ras->adev);

	list_for_each_entry(remote_adev, device_list_handle, gmc.xgmi.head) {

		amdgpu_ras_log_on_err_counter(remote_adev);

	}



	if (amdgpu_device_should_recover_gpu(ras->adev))

		amdgpu_device_gpu_recover(ras->adev, 0);

drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c

+16 −9
Original line number Diff line number Diff line
@@ -279,7 +279,7 @@ static const struct soc15_reg_golden golden_settings_gc_10_1_2_nv12[] = 


#define DEFAULT_SH_MEM_CONFIG \

	((SH_MEM_ADDRESS_MODE_64 << SH_MEM_CONFIG__ADDRESS_MODE__SHIFT) | \

	 (SH_MEM_ALIGNMENT_MODE_UNALIGNED << SH_MEM_CONFIG__ALIGNMENT_MODE__SHIFT) | \

	 (SH_MEM_ALIGNMENT_MODE_DWORD << SH_MEM_CONFIG__ALIGNMENT_MODE__SHIFT) | \

	 (SH_MEM_RETRY_MODE_ALL << SH_MEM_CONFIG__RETRY_MODE__SHIFT) | \

	 (3 << SH_MEM_CONFIG__INITIAL_INST_PREFETCH__SHIFT))
@@ -4104,6 +4104,12 @@ static void gfx_v10_0_update_medium_grain_clock_gating(struct amdgpu_device *ade 


	/* It is disabled by HW by default */

	if (enable && (adev->cg_flags & AMD_CG_SUPPORT_GFX_MGCG)) {

		/* 0 - Disable some blocks' MGCG */

		WREG32_SOC15(GC, 0, mmGRBM_GFX_INDEX, 0xe0000000);

		WREG32_SOC15(GC, 0, mmCGTT_WD_CLK_CTRL, 0xff000000);

		WREG32_SOC15(GC, 0, mmCGTT_VGT_CLK_CTRL, 0xff000000);

		WREG32_SOC15(GC, 0, mmCGTT_IA_CLK_CTRL, 0xff000000);



		/* 1 - RLC_CGTT_MGCG_OVERRIDE */

		def = data = RREG32_SOC15(GC, 0, mmRLC_CGTT_MGCG_OVERRIDE);

		data &= ~(RLC_CGTT_MGCG_OVERRIDE__GRBM_CGTT_SCLK_OVERRIDE_MASK |
@@ -4143,19 +4149,20 @@ static void gfx_v10_0_update_medium_grain_clock_gating(struct amdgpu_device *ade 
		if (def != data)

			WREG32_SOC15(GC, 0, mmRLC_CGTT_MGCG_OVERRIDE, data);



		/* 2 - disable MGLS in RLC */

		/* 2 - disable MGLS in CP */

		data = RREG32_SOC15(GC, 0, mmCP_MEM_SLP_CNTL);

		if (data & CP_MEM_SLP_CNTL__CP_MEM_LS_EN_MASK) {

			data &= ~CP_MEM_SLP_CNTL__CP_MEM_LS_EN_MASK;

			WREG32_SOC15(GC, 0, mmCP_MEM_SLP_CNTL, data);

		}



		/* 3 - disable MGLS in RLC */

		data = RREG32_SOC15(GC, 0, mmRLC_MEM_SLP_CNTL);

		if (data & RLC_MEM_SLP_CNTL__RLC_MEM_LS_EN_MASK) {

			data &= ~RLC_MEM_SLP_CNTL__RLC_MEM_LS_EN_MASK;

			WREG32_SOC15(GC, 0, mmRLC_MEM_SLP_CNTL, data);

		}



		/* 3 - disable MGLS in CP */

		data = RREG32_SOC15(GC, 0, mmCP_MEM_SLP_CNTL);

		if (data & CP_MEM_SLP_CNTL__CP_MEM_LS_EN_MASK) {

			data &= ~CP_MEM_SLP_CNTL__CP_MEM_LS_EN_MASK;

			WREG32_SOC15(GC, 0, mmCP_MEM_SLP_CNTL, data);

		}

	}

}
@@ -4266,7 +4273,7 @@ static int gfx_v10_0_update_gfx_clock_gating(struct amdgpu_device *adev, 
		/* ===  CGCG /CGLS for GFX 3D Only === */

		gfx_v10_0_update_3d_clock_gating(adev, enable);

		/* ===  MGCG + MGLS === */

		gfx_v10_0_update_medium_grain_clock_gating(adev, enable);

		/* gfx_v10_0_update_medium_grain_clock_gating(adev, enable); */

	}



	if (adev->cg_flags &

CRA Git | Maintained and supported by SUSTech CRA and CCSE