Commit 21ab095c authored Mar 07, 2019 by Sergei Shtylyov Committed by Geert Uytterhoeven Apr 02, 2019

clk: renesas: r8a77980: Fix RPC-IF module clock's parent

Testing has shown that the RPC-IF module clock's parent is the RPCD2
clock, not the RPC one -- the RPC-IF register reads stall otherwise...

Fixes: 94e3935b ("clk: renesas: r8a77980: Add RPC clocks")
Signed-off-by: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com>
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>

parent 3c14505c

drivers/clk/renesas/r8a77980-cpg-mssr.c

+1 −1

Original line number	Diff line number	Diff line
		@@ -171,7 +171,7 @@ static const struct mssr_mod_clk r8a77980_mod_clks[] __initconst = {
		DEF_MOD("gpio1", 911, R8A77980_CLK_CP),
		DEF_MOD("gpio0", 912, R8A77980_CLK_CP),
		DEF_MOD("can-fd", 914, R8A77980_CLK_S3D2),
		DEF_MOD("rpc-if", 917, R8A77980_CLK_RPC),
		DEF_MOD("rpc-if", 917, R8A77980_CLK_RPCD2),
		DEF_MOD("i2c4", 927, R8A77980_CLK_S0D6),
		DEF_MOD("i2c3", 928, R8A77980_CLK_S0D6),
		DEF_MOD("i2c2", 929, R8A77980_CLK_S3D2),