Commit 21a92676 authored Jan 07, 2020 by Marcel Ziswiler Committed by Lorenzo Pieralisi Jan 10, 2020

PCI: tegra: Fix afi_pex2_ctrl reg offset for Tegra30



Fix AFI_PEX2_CTRL reg offset for Tegra30 by moving it from the Tegra20
SoC struct where it erroneously got added. This fixes the AFI_PEX2_CTRL
reg offset being uninitialised subsequently failing to bring up the
third PCIe port.

Fixes: adb2653b ("PCI: tegra: Add AFI_PEX2_CTRL reg offset as part of SoC struct")
Signed-off-by: Marcel Ziswiler <marcel@ziswiler.com>
Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
Reviewed-by: Andrew Murray <andrew.murray@arm.com>
Acked-by: Thierry Reding <treding@nvidia.com>

parent 88519914

drivers/pci/controller/pci-tegra.c

+1 −1

Original line number	Diff line number	Diff line
		@@ -2499,7 +2499,6 @@ static const struct tegra_pcie_soc tegra20_pcie = {
		.num_ports = 2,
		.ports = tegra20_pcie_ports,
		.msi_base_shift = 0,
		.afi_pex2_ctrl = 0x128,
		.pads_pll_ctl = PADS_PLL_CTL_TEGRA20,
		.tx_ref_sel = PADS_PLL_CTL_TXCLKREF_DIV10,
		.pads_refclk_cfg0 = 0xfa5cfa5c,
		@@ -2528,6 +2527,7 @@ static const struct tegra_pcie_soc tegra30_pcie = {
		.num_ports = 3,
		.ports = tegra30_pcie_ports,
		.msi_base_shift = 8,
		.afi_pex2_ctrl = 0x128,
		.pads_pll_ctl = PADS_PLL_CTL_TEGRA30,
		.tx_ref_sel = PADS_PLL_CTL_TXCLKREF_BUF_EN,
		.pads_refclk_cfg0 = 0xfa5cfa5c,

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