Merge tag 'v5.6-next-dts32' of... (21a3c5dd) · Commits · 戴 / test

arch/arm/boot/dts/mt2701.dtsi

+1 −1

Original line number	Diff line number	Diff line
		@@ -148,7 +148,7 @@
		reg = <0 0x10005000 0 0x1000>;
		};

		scpsys: scpsys@10006000 {
		scpsys: power-controller@10006000 {
		compatible = "mediatek,mt2701-scpsys", "syscon";
		#power-domain-cells = <1>;
		reg = <0 0x10006000 0 0x1000>;

+1 −1

Original line number	Diff line number	Diff line
		@@ -268,7 +268,7 @@
		reg = <0 0x10005000 0 0x1000>;
		};

		scpsys: scpsys@10006000 {
		scpsys: power-controller@10006000 {
		compatible = "mediatek,mt7623-scpsys",
		"mediatek,mt2701-scpsys",
		"syscon";

+15 −1

Original line number	Diff line number	Diff line
		@@ -90,7 +90,7 @@
		#clock-cells = <1>;
		};

		scpsys: scpsys@10006000 {
		scpsys: power-controller@10006000 {
		compatible = "mediatek,mt7629-scpsys",
		"mediatek,mt7622-scpsys";
		#power-domain-cells = <1>;
		@@ -241,6 +241,20 @@
		status = "disabled";
		};

		pwm: pwm@11006000 {
		compatible = "mediatek,mt7629-pwm";
		reg = <0x11006000 0x1000>;
		#pwm-cells = <2>;
		clocks = <&topckgen CLK_TOP_PWM_SEL>,
		<&pericfg CLK_PERI_PWM_PD>,
		<&pericfg CLK_PERI_PWM1_PD>;
		clock-names = "top", "main", "pwm1";
		assigned-clocks = <&topckgen CLK_TOP_PWM_SEL>;
		assigned-clock-parents =
		<&topckgen CLK_TOP_UNIVPLL2_D4>;
		status = "disabled";
		};

		i2c: i2c@11007000 {
		compatible = "mediatek,mt7629-i2c",
		"mediatek,mt2712-i2c";