drm/amdgpu/gmc7: drop fb location programming (219611db) · Commits · 戴 / test

drivers/gpu/drm/amd/amdgpu/gmc_v7_0.c

+0 −13

Original line number	Diff line number	Diff line
		@@ -266,7 +266,6 @@ static void gmc_v7_0_vram_gtt_location(struct amdgpu_device *adev,
		*/
		static void gmc_v7_0_mc_program(struct amdgpu_device *adev)
		{
		struct amdgpu_mode_mc_save save;
		u32 tmp;
		int i, j;

		@@ -280,10 +279,6 @@ static void gmc_v7_0_mc_program(struct amdgpu_device *adev)
		}
		WREG32(mmHDP_REG_COHERENCY_FLUSH_CNTL, 0);

		if (adev->mode_info.num_crtc)
		amdgpu_display_set_vga_render_state(adev, false);

		gmc_v7_0_mc_stop(adev, &save);
		if (gmc_v7_0_wait_for_idle((void *)adev)) {
		dev_warn(adev->dev, "Wait for MC idle timedout !\n");
		}
		@@ -294,20 +289,12 @@ static void gmc_v7_0_mc_program(struct amdgpu_device *adev)
		adev->mc.vram_end >> 12);
		WREG32(mmMC_VM_SYSTEM_APERTURE_DEFAULT_ADDR,
		adev->vram_scratch.gpu_addr >> 12);
		tmp = ((adev->mc.vram_end >> 24) & 0xFFFF) << 16;
		tmp \|= ((adev->mc.vram_start >> 24) & 0xFFFF);
		WREG32(mmMC_VM_FB_LOCATION, tmp);
		/* XXX double check these! */
		WREG32(mmHDP_NONSURFACE_BASE, (adev->mc.vram_start >> 8));
		WREG32(mmHDP_NONSURFACE_INFO, (2 << 7) \| (1 << 30));
		WREG32(mmHDP_NONSURFACE_SIZE, 0x3FFFFFFF);
		WREG32(mmMC_VM_AGP_BASE, 0);
		WREG32(mmMC_VM_AGP_TOP, 0x0FFFFFFF);
		WREG32(mmMC_VM_AGP_BOT, 0x0FFFFFFF);
		if (gmc_v7_0_wait_for_idle((void *)adev)) {
		dev_warn(adev->dev, "Wait for MC idle timedout !\n");
		}
		gmc_v7_0_mc_resume(adev, &save);

		WREG32(mmBIF_FB_EN, BIF_FB_EN__FB_READ_EN_MASK \| BIF_FB_EN__FB_WRITE_EN_MASK);