Commit 21954712 authored by Olof Johansson's avatar Olof Johansson
Browse files

Merge tag 'tegra-for-5.2-memory' of... 

Merge tag 'tegra-for-5.2-memory' of git://git.kernel.org/pub/scm/linux/kernel/git/tegra/linux into arm/drivers

memory: tegra: Changes for v5.2-rc1

These are a set of fixes for various issues related to the Tegra memory
controller.

* tag 'tegra-for-5.2-memory' of git://git.kernel.org/pub/scm/linux/kernel/git/tegra/linux

:
  memory: tegra: Fix a typos for "fdcdwr2" mc client
  Revert "ARM: tegra: Restore memory arbitration on resume from LP1 on Tegra30+"
  memory: tegra: Replace readl-writel with mc_readl-mc_writel
  memory: tegra: Fix integer overflow on tick value calculation
  memory: tegra: Fix missed registers values latching
  memory: tegra: Properly spell "tegra"
  memory: tegra: Make terga20_mc_reset_ops static

Signed-off-by: default avatarOlof Johansson <olof@lixom.net>
parents 990d4322 67a8d5b0

arch/arm/mach-tegra/iomap.h

+0 −9
Original line number Diff line number Diff line
@@ -79,24 +79,15 @@ 
#define TEGRA_PMC_BASE			0x7000E400

#define TEGRA_PMC_SIZE			SZ_256



#define TEGRA_MC_BASE			0x7000F000

#define TEGRA_MC_SIZE			SZ_1K



#define TEGRA_EMC_BASE			0x7000F400

#define TEGRA_EMC_SIZE			SZ_1K



#define TEGRA114_MC_BASE		0x70019000

#define TEGRA114_MC_SIZE		SZ_4K



#define TEGRA_EMC0_BASE			0x7001A000

#define TEGRA_EMC0_SIZE			SZ_2K



#define TEGRA_EMC1_BASE			0x7001A800

#define TEGRA_EMC1_SIZE			SZ_2K



#define TEGRA124_MC_BASE		0x70019000

#define TEGRA124_MC_SIZE		SZ_4K



#define TEGRA124_EMC_BASE		0x7001B000

#define TEGRA124_EMC_SIZE		SZ_2K

arch/arm/mach-tegra/sleep-tegra30.S

+0 −21
Original line number Diff line number Diff line
@@ -44,8 +44,6 @@ 
#define EMC_XM2VTTGENPADCTRL		0x310

#define EMC_XM2VTTGENPADCTRL2		0x314



#define MC_EMEM_ARB_CFG			0x90



#define PMC_CTRL			0x0

#define PMC_CTRL_SIDE_EFFECT_LP0 (1 << 14) /* enter LP0 when CPU pwr gated */
@@ -420,22 +418,6 @@ _pll_m_c_x_done: 
	movweq	r0, #:lower16:TEGRA124_EMC_BASE

	movteq	r0, #:upper16:TEGRA124_EMC_BASE



	cmp	r10, #TEGRA30

	moveq	r2, #0x20

	movweq	r4, #:lower16:TEGRA_MC_BASE

	movteq	r4, #:upper16:TEGRA_MC_BASE

	cmp	r10, #TEGRA114

	moveq	r2, #0x34

	movweq	r4, #:lower16:TEGRA114_MC_BASE

	movteq	r4, #:upper16:TEGRA114_MC_BASE

	cmp	r10, #TEGRA124

	moveq	r2, #0x20

	movweq	r4, #:lower16:TEGRA124_MC_BASE

	movteq	r4, #:upper16:TEGRA124_MC_BASE



	ldr	r1, [r5, r2]		@ restore MC_EMEM_ARB_CFG

	str	r1, [r4, #MC_EMEM_ARB_CFG]



exit_self_refresh:

	ldr	r1, [r5, #0xC]		@ restore EMC_XM2VTTGENPADCTRL

	str	r1, [r0, #EMC_XM2VTTGENPADCTRL]
@@ -564,7 +546,6 @@ tegra30_sdram_pad_address: 
	.word	TEGRA_PMC_BASE + PMC_IO_DPD_STATUS			@0x14

	.word	TEGRA_CLK_RESET_BASE + CLK_RESET_CLK_SOURCE_MSELECT	@0x18

	.word	TEGRA_CLK_RESET_BASE + CLK_RESET_SCLK_BURST		@0x1c

	.word	TEGRA_MC_BASE + MC_EMEM_ARB_CFG				@0x20

tegra30_sdram_pad_address_end:



tegra114_sdram_pad_address:
@@ -581,7 +562,6 @@ tegra114_sdram_pad_address: 
	.word	TEGRA_EMC1_BASE + EMC_AUTO_CAL_INTERVAL			@0x28

	.word	TEGRA_EMC1_BASE + EMC_XM2VTTGENPADCTRL			@0x2c

	.word	TEGRA_EMC1_BASE + EMC_XM2VTTGENPADCTRL2			@0x30

	.word	TEGRA114_MC_BASE + MC_EMEM_ARB_CFG			@0x34

tegra114_sdram_pad_adress_end:



tegra124_sdram_pad_address:
@@ -593,7 +573,6 @@ tegra124_sdram_pad_address: 
	.word	TEGRA_PMC_BASE + PMC_IO_DPD_STATUS			@0x14

	.word	TEGRA_CLK_RESET_BASE + CLK_RESET_CLK_SOURCE_MSELECT	@0x18

	.word	TEGRA_CLK_RESET_BASE + CLK_RESET_SCLK_BURST		@0x1c

	.word	TEGRA124_MC_BASE + MC_EMEM_ARB_CFG			@0x20

tegra124_sdram_pad_address_end:



tegra30_sdram_pad_size:

drivers/memory/tegra/mc.c

+20 −14
Original line number Diff line number Diff line
@@ -51,6 +51,9 @@ 
#define MC_EMEM_ADR_CFG 0x54

#define MC_EMEM_ADR_CFG_EMEM_NUMDEV BIT(0)



#define MC_TIMING_CONTROL		0xfc

#define MC_TIMING_UPDATE		BIT(0)



static const struct of_device_id tegra_mc_of_match[] = {

#ifdef CONFIG_ARCH_TEGRA_2x_SOC

	{ .compatible = "nvidia,tegra20-mc-gart", .data = &tegra20_mc_soc },
@@ -74,7 +77,7 @@ static const struct of_device_id tegra_mc_of_match[] = { 
};

MODULE_DEVICE_TABLE(of, tegra_mc_of_match);



static int terga_mc_block_dma_common(struct tegra_mc *mc,

static int tegra_mc_block_dma_common(struct tegra_mc *mc,

				     const struct tegra_mc_reset *rst)

{

	unsigned long flags;
@@ -90,13 +93,13 @@ static int terga_mc_block_dma_common(struct tegra_mc *mc, 
	return 0;

}



static bool terga_mc_dma_idling_common(struct tegra_mc *mc,

static bool tegra_mc_dma_idling_common(struct tegra_mc *mc,

				       const struct tegra_mc_reset *rst)

{

	return (mc_readl(mc, rst->status) & BIT(rst->bit)) != 0;

}



static int terga_mc_unblock_dma_common(struct tegra_mc *mc,

static int tegra_mc_unblock_dma_common(struct tegra_mc *mc,

				       const struct tegra_mc_reset *rst)

{

	unsigned long flags;
@@ -112,17 +115,17 @@ static int terga_mc_unblock_dma_common(struct tegra_mc *mc, 
	return 0;

}



static int terga_mc_reset_status_common(struct tegra_mc *mc,

static int tegra_mc_reset_status_common(struct tegra_mc *mc,

					const struct tegra_mc_reset *rst)

{

	return (mc_readl(mc, rst->control) & BIT(rst->bit)) != 0;

}



const struct tegra_mc_reset_ops terga_mc_reset_ops_common = {

	.block_dma = terga_mc_block_dma_common,

	.dma_idling = terga_mc_dma_idling_common,

	.unblock_dma = terga_mc_unblock_dma_common,

	.reset_status = terga_mc_reset_status_common,

const struct tegra_mc_reset_ops tegra_mc_reset_ops_common = {

	.block_dma = tegra_mc_block_dma_common,

	.dma_idling = tegra_mc_dma_idling_common,

	.unblock_dma = tegra_mc_unblock_dma_common,

	.reset_status = tegra_mc_reset_status_common,

};



static inline struct tegra_mc *reset_to_mc(struct reset_controller_dev *rcdev)
@@ -282,25 +285,28 @@ static int tegra_mc_setup_latency_allowance(struct tegra_mc *mc) 
	u32 value;



	/* compute the number of MC clock cycles per tick */

	tick = mc->tick * clk_get_rate(mc->clk);

	tick = (unsigned long long)mc->tick * clk_get_rate(mc->clk);

	do_div(tick, NSEC_PER_SEC);



	value = readl(mc->regs + MC_EMEM_ARB_CFG);

	value = mc_readl(mc, MC_EMEM_ARB_CFG);

	value &= ~MC_EMEM_ARB_CFG_CYCLES_PER_UPDATE_MASK;

	value |= MC_EMEM_ARB_CFG_CYCLES_PER_UPDATE(tick);

	writel(value, mc->regs + MC_EMEM_ARB_CFG);

	mc_writel(mc, value, MC_EMEM_ARB_CFG);



	/* write latency allowance defaults */

	for (i = 0; i < mc->soc->num_clients; i++) {

		const struct tegra_mc_la *la = &mc->soc->clients[i].la;

		u32 value;



		value = readl(mc->regs + la->reg);

		value = mc_readl(mc, la->reg);

		value &= ~(la->mask << la->shift);

		value |= (la->def & la->mask) << la->shift;

		writel(value, mc->regs + la->reg);

		mc_writel(mc, value, la->reg);

	}



	/* latch new values */

	mc_writel(mc, MC_TIMING_UPDATE, MC_TIMING_CONTROL);



	return 0;

}

drivers/memory/tegra/mc.h

+1 −1
Original line number Diff line number Diff line
@@ -35,7 +35,7 @@ static inline void mc_writel(struct tegra_mc *mc, u32 value, 
	writel_relaxed(value, mc->regs + offset);

}



extern const struct tegra_mc_reset_ops terga_mc_reset_ops_common;

extern const struct tegra_mc_reset_ops tegra_mc_reset_ops_common;



#ifdef CONFIG_ARCH_TEGRA_2x_SOC

extern const struct tegra_mc_soc tegra20_mc_soc;

drivers/memory/tegra/tegra114.c

+2 −2
Original line number Diff line number Diff line
@@ -572,7 +572,7 @@ static const struct tegra_mc_client tegra114_mc_clients[] = { 
		},

	}, {

		.id = 0x34,

		.name = "fdcwr2",

		.name = "fdcdwr2",

		.swgroup = TEGRA_SWGROUP_NV,

		.smmu = {

			.reg = 0x22c,
@@ -975,7 +975,7 @@ const struct tegra_mc_soc tegra114_mc_soc = { 
	.smmu = &tegra114_smmu_soc,

	.intmask = MC_INT_INVALID_SMMU_PAGE | MC_INT_SECURITY_VIOLATION |

		   MC_INT_DECERR_EMEM,

	.reset_ops = &terga_mc_reset_ops_common,

	.reset_ops = &tegra_mc_reset_ops_common,

	.resets = tegra114_mc_resets,

	.num_resets = ARRAY_SIZE(tegra114_mc_resets),

};

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