Commit 216883a4 authored by Olof Johansson's avatar Olof Johansson
Browse files

Merge tag 'renesas-dt-for-v4.3' of...

Merge tag 'renesas-dt-for-v4.3' of git://git.kernel.org/pub/scm/linux/kernel/git/horms/renesas into next/dt

Merge "Renesas ARM Based SoC DT Updates for v4.3" from Simon Horman:

* Configure IRLM mode via DT on r8a7779 SoC
* Use "arm,gic-400" for GIC on r8a777[01349] and r8a73a4 SoCs
* Add pinctrl and gpio-hog for lcdc0 to armadillo800eva board
* EtherAVB DT support for r8a7790 SoC
* Minimal device tree for r8a7793 SoC and its Gose board

* tag 'renesas-dt-for-v4.3' of git://git.kernel.org/pub/scm/linux/kernel/git/horms/renesas:
  ARM: shmobile: r8a7779: Configure IRLM mode via DT
  ARM: shmobile: r8a7794 dtsi: Use "arm,gic-400" for GIC
  ARM: shmobile: r8a7793 dtsi: Use "arm,gic-400" for GIC
  ARM: shmobile: r8a7791 dtsi: Use "arm,gic-400" for GIC
  ARM: shmobile: r8a7790 dtsi: Use "arm,gic-400" for GIC
  ARM: shmobile: r8a73a4 dtsi: Use "arm,gic-400" for GIC
  ARM: shmobile: armadillo800eva dts: Add pinctrl and gpio-hog for lcdc0
  ARM: shmobile: r8a7790: add EtherAVB DT support
  ARM: shmobile: r8a7790: add EtherAVB clocks
  ARM: shmobile: r8a7793: add minimal Gose board device tree
  ARM: shmobile: add r8a7793 minimal SoC device tree
parents 3fbf02a8 7bf46d0b
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+1 −0
Original line number Diff line number Diff line
@@ -516,6 +516,7 @@ dtb-$(CONFIG_ARCH_SHMOBILE_MULTI) += \
	r8a7790-lager.dtb \
	r8a7791-henninger.dtb \
	r8a7791-koelsch.dtb \
	r8a7793-gose.dtb \
	r8a7794-alt.dtb \
	sh73a0-kzm9g.dtb
dtb-$(CONFIG_ARCH_SOCFPGA) += \
+1 −1
Original line number Diff line number Diff line
@@ -434,7 +434,7 @@
	};

	gic: interrupt-controller@f1001000 {
		compatible = "arm,cortex-a15-gic";
		compatible = "arm,gic-400";
		#interrupt-cells = <3>;
		#address-cells = <0>;
		interrupt-controller;
+13 −0
Original line number Diff line number Diff line
@@ -224,6 +224,9 @@
};

&pfc {
	pinctrl-0 = <&lcd0_pins>;
	pinctrl-names = "default";

	ether_pins: ether {
		renesas,groups = "gether_mii", "gether_int";
		renesas,function = "gether";
@@ -259,6 +262,16 @@
				 "fsia_data_in_1", "fsia_data_out_0";
		renesas,function = "fsia";
	};

	lcd0_pins: lcd0 {
		renesas,groups = "lcd0_data24_0", "lcd0_lclk_1", "lcd0_sync";
		renesas,function = "lcd0";

		/* DBGMD/LCDC0/FSIA MUX */
		gpio-hog;
		gpios = <176 0>;
		output-high;
	};
};

&tpu {
+3 −2
Original line number Diff line number Diff line
@@ -148,7 +148,7 @@
		interrupt-controller;
	};

	irqpin0: interrupt-controller@fe780010 {
	irqpin0: interrupt-controller@fe78001c {
		compatible = "renesas,intc-irqpin-r8a7779", "renesas,intc-irqpin";
		#interrupt-cells = <2>;
		status = "disabled";
@@ -157,7 +157,8 @@
			<0xfe780010 4>,
			<0xfe780024 4>,
			<0xfe780044 4>,
			<0xfe780064 4>;
			<0xfe780064 4>,
			<0xfe780000 4>;
		interrupts = <0 27 IRQ_TYPE_LEVEL_HIGH
			      0 28 IRQ_TYPE_LEVEL_HIGH
			      0 29 IRQ_TYPE_LEVEL_HIGH
+17 −5
Original line number Diff line number Diff line
@@ -113,7 +113,7 @@
	};

	gic: interrupt-controller@f1001000 {
		compatible = "arm,cortex-a15-gic";
		compatible = "arm,gic-400";
		#interrupt-cells = <3>;
		#address-cells = <0>;
		interrupt-controller;
@@ -671,6 +671,16 @@
		status = "disabled";
	};

	avb: ethernet@e6800000 {
		compatible = "renesas,etheravb-r8a7790";
		reg = <0 0xe6800000 0 0x800>, <0 0xee0e8000 0 0x4000>;
		interrupts = <0 163 IRQ_TYPE_LEVEL_HIGH>;
		clocks = <&mstp8_clks R8A7790_CLK_ETHERAVB>;
		#address-cells = <1>;
		#size-cells = <0>;
		status = "disabled";
	};

	sata0: sata@ee300000 {
		compatible = "renesas,sata-r8a7790";
		reg = <0 0xee300000 0 0x2000>;
@@ -1249,16 +1259,18 @@
			compatible = "renesas,r8a7790-mstp-clocks", "renesas,cpg-mstp-clocks";
			reg = <0 0xe6150990 0 4>, <0 0xe61509a0 0 4>;
			clocks = <&hp_clk>, <&zg_clk>, <&zg_clk>, <&zg_clk>,
			         <&zg_clk>, <&p_clk>, <&zs_clk>, <&zs_clk>;
			         <&zg_clk>, <&hp_clk>, <&p_clk>, <&zs_clk>,
				 <&zs_clk>;
			#clock-cells = <1>;
			clock-indices = <
				R8A7790_CLK_MLB R8A7790_CLK_VIN3 R8A7790_CLK_VIN2
				R8A7790_CLK_VIN1 R8A7790_CLK_VIN0 R8A7790_CLK_ETHER
				R8A7790_CLK_VIN1 R8A7790_CLK_VIN0
				R8A7790_CLK_ETHERAVB R8A7790_CLK_ETHER
				R8A7790_CLK_SATA1 R8A7790_CLK_SATA0
			>;
			clock-output-names =
				"mlb", "vin3", "vin2", "vin1", "vin0", "ether",
				"sata1", "sata0";
				"mlb", "vin3", "vin2", "vin1", "vin0",
				"etheravb", "ether", "sata1", "sata0";
		};
		mstp9_clks: mstp9_clks@e6150994 {
			compatible = "renesas,r8a7790-mstp-clocks", "renesas,cpg-mstp-clocks";
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