Commit 2142baba authored by Linus Torvalds's avatar Linus Torvalds
Browse files

Merge master.kernel.org:/home/rmk/linux-2.6-arm 

* master.kernel.org:/home/rmk/linux-2.6-arm: (45 commits)
  [ARM] 5489/1: ARM errata: Data written to the L2 cache can be overwritten with stale data
  [ARM] 5490/1: ARM errata: Processor deadlock when a false hazard is created
  [ARM] 5487/1: ARM errata: Stale prediction on replaced interworking branch
  [ARM] 5488/1: ARM errata: Invalidation of the Instruction Cache operation can fail
  davinci: DM644x: NAND: update partitioning
  davinci: update DM644x support in preparation for more SoCs
  davinci: DM644x: rename board file
  davinci: update pin-multiplexing support
  davinci: serial: generalize for more SoCs
  davinci: DM355 IRQ Definitions
  davinci: DM646x: add interrupt number and priorities
  davinci: PSC: Clear bits in MDCTL reg before setting new bits
  davinci: gpio bugfixes
  davinci: add EDMA driver
  davinci: timers: use clk_get_rate()
  [ARM] pxa/littleton: add missing da9034 touchscreen support
  [ARM] pxa/zylonite: configure GPIO18/19 correctly, used by 2 GPIO expanders
  [ARM] pxa/zylonite: fix the issue of unused SDATA_IN_1 pin get AC97 not working
  [ARM] pxa: make ads7846 on corgi and spitz to sync on HSYNC
  [ARM] pxa: remove unused CPU_FREQ_PXA Kconfig symbol
  ...
parents bb402c4f 0516e464

arch/arm/Kconfig

+52 −8
Original line number Diff line number Diff line
@@ -486,8 +486,6 @@ config ARCH_PXA 
	select HAVE_CLK

	select COMMON_CLKDEV

	select ARCH_REQUIRE_GPIOLIB

	select HAVE_CLK

	select COMMON_CLKDEV

	select GENERIC_TIME

	select GENERIC_CLOCKEVENTS

	select TICK_ONESHOT
@@ -585,6 +583,8 @@ config ARCH_DAVINCI 
	select ARCH_REQUIRE_GPIOLIB

	select HAVE_CLK

	select ZONE_DMA

	select HAVE_IDE

	select COMMON_CLKDEV

	help

	  Support for TI's DaVinci platform.
@@ -740,6 +740,56 @@ if !MMU 
source "arch/arm/Kconfig-nommu"

endif



config ARM_ERRATA_411920

	bool "ARM errata: Invalidation of the Instruction Cache operation can fail"

	depends on CPU_V6 && !SMP

	help

	  Invalidation of the Instruction Cache operation can

	  fail. This erratum is present in 1136 (before r1p4), 1156 and 1176.

	  It does not affect the MPCore. This option enables the ARM Ltd.

	  recommended workaround.



config ARM_ERRATA_430973

	bool "ARM errata: Stale prediction on replaced interworking branch"

	depends on CPU_V7

	help

	  This option enables the workaround for the 430973 Cortex-A8

	  (r1p0..r1p2) erratum. If a code sequence containing an ARM/Thumb

	  interworking branch is replaced with another code sequence at the

	  same virtual address, whether due to self-modifying code or virtual

	  to physical address re-mapping, Cortex-A8 does not recover from the

	  stale interworking branch prediction. This results in Cortex-A8

	  executing the new code sequence in the incorrect ARM or Thumb state.

	  The workaround enables the BTB/BTAC operations by setting ACTLR.IBE

	  and also flushes the branch target cache at every context switch.

	  Note that setting specific bits in the ACTLR register may not be

	  available in non-secure mode.



config ARM_ERRATA_458693

	bool "ARM errata: Processor deadlock when a false hazard is created"

	depends on CPU_V7

	help

	  This option enables the workaround for the 458693 Cortex-A8 (r2p0)

	  erratum. For very specific sequences of memory operations, it is

	  possible for a hazard condition intended for a cache line to instead

	  be incorrectly associated with a different cache line. This false

	  hazard might then cause a processor deadlock. The workaround enables

	  the L1 caching of the NEON accesses and disables the PLD instruction

	  in the ACTLR register. Note that setting specific bits in the ACTLR

	  register may not be available in non-secure mode.



config ARM_ERRATA_460075

	bool "ARM errata: Data written to the L2 cache can be overwritten with stale data"

	depends on CPU_V7

	help

	  This option enables the workaround for the 460075 Cortex-A8 (r2p0)

	  erratum. Any asynchronous access to the L2 cache may encounter a

	  situation in which recent store transactions to the L2 cache are lost

	  and overwritten with stale memory contents from external memory. The

	  workaround disables the write-allocate mode for the L2 cache via the

	  ACTLR register. Note that setting specific bits in the ACTLR register

	  may not be available in non-secure mode.



endmenu



source "arch/arm/common/Kconfig"
@@ -1171,12 +1221,6 @@ config CPU_FREQ_IMX 


	  If in doubt, say N.



config CPU_FREQ_PXA

	bool

	depends on CPU_FREQ && ARCH_PXA && PXA25x

	default y

	select CPU_FREQ_DEFAULT_GOV_USERSPACE



endif



source "drivers/cpuidle/Kconfig"

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