Commit 2131f655 authored by Jun Lei's avatar Jun Lei Committed by Alex Deucher
Browse files

drm/amd/display: add support for forcing DCFCLK without affecting watermarks 



[why]
useful for debugging

[how]
plumb a debug option in dc

Signed-off-by: default avatarJun Lei <Jun.Lei@amd.com>
Reviewed-by: default avatarTony Cheng <Tony.Cheng@amd.com>
Acked-by: default avatarBhawanpreet Lakha <Bhawanpreet.Lakha@amd.com>
Signed-off-by: default avatarAlex Deucher <alexander.deucher@amd.com>
parent 6f4992b0

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn20/dcn20_clk_mgr.c

+4 −0
Original line number Diff line number Diff line
@@ -172,6 +172,10 @@ void dcn2_update_clocks(struct clk_mgr *clk_mgr_base, 
			pp_smu->set_voltage_by_freq(&pp_smu->pp_smu, PP_SMU_NV_PHYCLK, clk_mgr_base->clks.phyclk_khz / 1000);

	}



	if (dc->debug.force_min_dcfclk_mhz > 0)

		new_clocks->dcfclk_khz = (new_clocks->dcfclk_khz > (dc->debug.force_min_dcfclk_mhz * 1000)) ?

				new_clocks->dcfclk_khz : (dc->debug.force_min_dcfclk_mhz * 1000);



	if (should_set_clock(safe_to_lower, new_clocks->dcfclk_khz, clk_mgr_base->clks.dcfclk_khz)) {

		clk_mgr_base->clks.dcfclk_khz = new_clocks->dcfclk_khz;

		if (pp_smu && pp_smu->set_hard_min_dcfclk_by_freq)

drivers/gpu/drm/amd/display/dc/dc.h

+8 −0
Original line number Diff line number Diff line
@@ -369,6 +369,10 @@ struct dc_debug_options { 
#ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT

	bool disable_fec;

#endif

	/* This forces a hard min on the DCFCLK requested to SMU/PP

	 * watermarks are not affected.

	 */

	unsigned int force_min_dcfclk_mhz;

};



struct dc_debug_data {
@@ -418,6 +422,10 @@ struct dc_bounding_box_overrides { 
	int urgent_latency_ns;

	int percent_of_ideal_drambw;

	int dram_clock_change_latency_ns;

	/* This forces a hard min on the DCFCLK we use

	 * for DML.  Unlike the debug option for forcing

	 * DCFCLK, this override affects watermark calculations

	 */

	int min_dcfclk_mhz;

};

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