Commit 21310c39 authored Nov 21, 2018 by Neil Armstrong

clk: meson: Fix GXL HDMI PLL fractional bits width



The GXL Documentation specifies 12 bits for the Fractional bit field,
bit the last bits have a different purpose that we cannot handle right
now, so update the bitwidth to have correct fractional calculations.

Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
[narmstrong: added comment on GXL HHI_HDMI_PLL_CNTL register shift]
Acked-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com>
Link: https://lkml.kernel.org/r/20181121111922.1277-1-narmstrong@baylibre.com

parent a7d19b05

drivers/clk/meson/gxbb.c

+7 −1

Original line number	Diff line number	Diff line
		@@ -216,10 +216,16 @@ static struct clk_regmap gxl_hdmi_pll_dco = {
		.shift = 9,
		.width = 5,
		},
		/*
		* On gxl, there is a register shift due to
		* HHI_HDMI_PLL_CNTL1 which does not exist on gxbb,
		* so we use the HHI_HDMI_PLL_CNTL2 define from GXBB
		* instead which is defined at the same offset.
		*/
		.frac = {
		.reg_off = HHI_HDMI_PLL_CNTL2,
		.shift = 0,
		.width = 12,
		.width = 10,
		},
		.l = {
		.reg_off = HHI_HDMI_PLL_CNTL,

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