Commit 21170e3b authored by Stephen Boyd's avatar Stephen Boyd
Browse files

Merge branches 'clk-spreadtrum', 'clk-mvebu-dvfs', 'clk-qoriq', 'clk-imx' and... 

Merge branches 'clk-spreadtrum', 'clk-mvebu-dvfs', 'clk-qoriq', 'clk-imx' and 'clk-qcom-ipq8074' into clk-next

* clk-spreadtrum:
  clk: sprd: add clocks support for SC9860
  clk: sprd: Add dt-bindings include file for SC9860
  dt-bindings: Add Spreadtrum clock binding documentation
  clk: sprd: add adjustable pll support
  clk: sprd: add composite clock support
  clk: sprd: add divider clock support
  clk: sprd: add mux clock support
  clk: sprd: add gate clock support
  clk: sprd: Add common infrastructure
  clk: move clock common macros out from vendor directories

* clk-mvebu-dvfs:
  clk: mvebu: armada-37xx-periph: add DVFS support for cpu clocks
  clk: mvebu: armada-37xx-periph: prepare cpu clk to be used with DVFS
  clk: mvebu: armada-37xx-periph: cosmetic changes

* clk-qoriq:
  clk: qoriq: add more divider clocks support

* clk-imx:
  clk: imx51: uart4, uart5 gates only exist on imx50, imx53

* clk-qcom-ipq8074:
  clk: qcom: ipq8074: add misc resets for PCIE and NSS
  dt-bindings: clock: qcom: add misc resets for PCIE and NSS
  clk: qcom: ipq8074: add GP and Crypto clocks
  clk: qcom: ipq8074: add NSS ethernet port clocks
  clk: qcom: ipq8074: add NSS clocks
  clk: qcom: ipq8074: add PCIE, USB and SDCC clocks
  clk: qcom: ipq8074: add remaining PLL’s
  dt-bindings: clock: qcom: add remaining clocks for IPQ8074
  clk: qcom: ipq8074: fix missing GPLL0 divider width
  clk: qcom: add parent map for regmap mux
  clk: qcom: add read-only divider operations
parents 74b48999 a6ae1a29 2089dc33 36ab0467 59dc3d8c 7f41bd4a

Documentation/devicetree/bindings/clock/qoriq-clock.txt

+1 −0
Original line number Diff line number Diff line
@@ -78,6 +78,7 @@ second cell is the clock index for the specified type. 
	2	hwaccel		index (n in CLKCGnHWACSR)

	3	fman		0 for fm1, 1 for fm2

	4	platform pll	0=pll, 1=pll/2, 2=pll/3, 3=pll/4

				4=pll/5, 5=pll/6, 6=pll/7, 7=pll/8

	5	coreclk		must be 0



3. Example

Documentation/devicetree/bindings/clock/sprd.txt

0 → 100644
+63 −0
Original line number Diff line number Diff line 
Spreadtrum Clock Binding

------------------------



Required properties:

- compatible: should contain the following compatible strings:

	- "sprd,sc9860-pmu-gate"

	- "sprd,sc9860-pll"

	- "sprd,sc9860-ap-clk"

	- "sprd,sc9860-aon-prediv"

	- "sprd,sc9860-apahb-gate"

	- "sprd,sc9860-aon-gate"

	- "sprd,sc9860-aonsecure-clk"

	- "sprd,sc9860-agcp-gate"

	- "sprd,sc9860-gpu-clk"

	- "sprd,sc9860-vsp-clk"

	- "sprd,sc9860-vsp-gate"

	- "sprd,sc9860-cam-clk"

	- "sprd,sc9860-cam-gate"

	- "sprd,sc9860-disp-clk"

	- "sprd,sc9860-disp-gate"

	- "sprd,sc9860-apapb-gate"



- #clock-cells: must be 1



- clocks : Should be the input parent clock(s) phandle for the clock, this

	   property here just simply shows which clock group the clocks'

	   parents are in, since each clk node would represent many clocks

	   which are defined in the driver.  The detailed dependency

	   relationship (i.e. how many parents and which are the parents)

	   are implemented in driver code.



Optional properties:



- reg:	Contain the registers base address and length. It must be configured

	only if no 'sprd,syscon' under the node.



- sprd,syscon: phandle to the syscon which is in the same address area with

	       the clock, and so we can get regmap for the clocks from the

	       syscon device.



Example:



	pmu_gate: pmu-gate {

		compatible = "sprd,sc9860-pmu-gate";

		sprd,syscon = <&pmu_regs>;

		clocks = <&ext_26m>;

		#clock-cells = <1>;

	};



	pll: pll {

		compatible = "sprd,sc9860-pll";

		sprd,syscon = <&ana_regs>;

		clocks = <&pmu_gate 0>;

		#clock-cells = <1>;

	};



	ap_clk: clock-controller@20000000 {

		compatible = "sprd,sc9860-ap-clk";

		reg = <0 0x20000000 0 0x400>;

		clocks = <&ext_26m>, <&pll 0>,

			 <&pmu_gate 0>;

		#clock-cells = <1>;

	};

drivers/clk/Kconfig

+1 −0
Original line number Diff line number Diff line
@@ -236,6 +236,7 @@ source "drivers/clk/mvebu/Kconfig" 
source "drivers/clk/qcom/Kconfig"

source "drivers/clk/renesas/Kconfig"

source "drivers/clk/samsung/Kconfig"

source "drivers/clk/sprd/Kconfig"

source "drivers/clk/sunxi-ng/Kconfig"

source "drivers/clk/tegra/Kconfig"

source "drivers/clk/ti/Kconfig"

drivers/clk/Makefile

+1 −0
Original line number Diff line number Diff line
@@ -85,6 +85,7 @@ obj-$(CONFIG_COMMON_CLK_SAMSUNG) += samsung/ 
obj-$(CONFIG_ARCH_SIRF)			+= sirf/

obj-$(CONFIG_ARCH_SOCFPGA)		+= socfpga/

obj-$(CONFIG_PLAT_SPEAR)		+= spear/

obj-$(CONFIG_ARCH_SPRD)			+= sprd/

obj-$(CONFIG_ARCH_STI)			+= st/

obj-$(CONFIG_ARCH_SUNXI)		+= sunxi/

obj-$(CONFIG_ARCH_SUNXI)		+= sunxi-ng/

drivers/clk/clk-qoriq.c

+8 −1
Original line number Diff line number Diff line
@@ -41,7 +41,7 @@ struct clockgen_pll_div { 
};



struct clockgen_pll {

	struct clockgen_pll_div div[4];

	struct clockgen_pll_div div[8];

};



#define CLKSEL_VALID	1
@@ -1127,6 +1127,13 @@ static void __init create_one_pll(struct clockgen *cg, int idx) 
		struct clk *clk;

		int ret;



		/*

		 * For platform PLL, there are 8 divider clocks.

		 * For core PLL, there are 4 divider clocks at most.

		 */

		if (idx != PLATFORM_PLL && i >= 4)

			break;



		snprintf(pll->div[i].name, sizeof(pll->div[i].name),

			 "cg-pll%d-div%d", idx, i + 1);

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