Commit 20f2ffe5 authored by Alex Deucher's avatar Alex Deucher
Browse files

drm/amdgpu: fold CONFIG_DRM_AMD_DC_DCN3* into CONFIG_DRM_AMD_DC_DCN (v3) 



Avoids confusion in configurations.

v2: fix build when CONFIG_DRM_AMD_DC_DCN is disabled
v3: rebase on latest code

Reviewed-by: Luben Tuikov <luben.tuikov@amd.com> (v1)
Signed-off-by: default avatarAlex Deucher <alexander.deucher@amd.com>
parent aeee2a48

drivers/gpu/drm/amd/amdgpu/amdgpu_device.c

+0 −2
Original line number Diff line number Diff line
@@ -3004,8 +3004,6 @@ bool amdgpu_device_asic_has_dc_support(enum amd_asic_type asic_type) 
	case CHIP_NAVI14:

	case CHIP_NAVI12:

	case CHIP_RENOIR:

#endif

#if defined(CONFIG_DRM_AMD_DC_DCN3_0)

	case CHIP_SIENNA_CICHLID:

	case CHIP_NAVY_FLOUNDER:

	case CHIP_DIMGREY_CAVEFISH:

drivers/gpu/drm/amd/display/Kconfig

+1 −26
Original line number Diff line number Diff line
@@ -15,32 +15,7 @@ config DRM_AMD_DC 
config DRM_AMD_DC_DCN

	def_bool n

	help

	  Raven, Navi and Renoir family support for display engine



config DRM_AMD_DC_DCN3_0

        bool "DCN 3.0 family"

        depends on DRM_AMD_DC && X86

        depends on DRM_AMD_DC_DCN

        help

            Choose this option if you want to have

            sienna_cichlid support for display engine



config DRM_AMD_DC_DCN3_01

	bool "DCN 3.01 family"

	depends on DRM_AMD_DC && X86

	depends on DRM_AMD_DC_DCN

	depends on DRM_AMD_DC_DCN3_0

	help

	    Choose this option if you want to have

	    Van Gogh support for display engine



config DRM_AMD_DC_DCN3_02

        bool "DCN 3.02 family"

        depends on DRM_AMD_DC_DCN3_0

        depends on DRM_AMD_DC_DCN3_01

        help

            Choose this option if you want to have

            Dimgrey_cavefish support for display engine

	  Raven, Navi, and newer family support for display engine



config DRM_AMD_DC_HDCP

	bool "Enable HDCP support in DC"

drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c

+3 −43
Original line number Diff line number Diff line
@@ -95,22 +95,16 @@ 


#define FIRMWARE_RENOIR_DMUB "amdgpu/renoir_dmcub.bin"

MODULE_FIRMWARE(FIRMWARE_RENOIR_DMUB);

#if defined(CONFIG_DRM_AMD_DC_DCN3_0)

#define FIRMWARE_SIENNA_CICHLID_DMUB "amdgpu/sienna_cichlid_dmcub.bin"

MODULE_FIRMWARE(FIRMWARE_SIENNA_CICHLID_DMUB);

#define FIRMWARE_NAVY_FLOUNDER_DMUB "amdgpu/navy_flounder_dmcub.bin"

MODULE_FIRMWARE(FIRMWARE_NAVY_FLOUNDER_DMUB);

#endif

#define FIRMWARE_GREEN_SARDINE_DMUB "amdgpu/green_sardine_dmcub.bin"

MODULE_FIRMWARE(FIRMWARE_GREEN_SARDINE_DMUB);

#if defined(CONFIG_DRM_AMD_DC_DCN3_01)

#define FIRMWARE_VANGOGH_DMUB "amdgpu/vangogh_dmcub.bin"

MODULE_FIRMWARE(FIRMWARE_VANGOGH_DMUB);

#endif

#if defined(CONFIG_DRM_AMD_DC_DCN3_02)

#define FIRMWARE_DIMGREY_CAVEFISH_DMUB "amdgpu/dimgrey_cavefish_dmcub.bin"

MODULE_FIRMWARE(FIRMWARE_DIMGREY_CAVEFISH_DMUB);

#endif



#define FIRMWARE_RAVEN_DMCU		"amdgpu/raven_dmcu.bin"

MODULE_FIRMWARE(FIRMWARE_RAVEN_DMCU);
@@ -1212,16 +1206,10 @@ static int load_dmcu_fw(struct amdgpu_device *adev) 
	case CHIP_NAVI10:

	case CHIP_NAVI14:

	case CHIP_RENOIR:

#if defined(CONFIG_DRM_AMD_DC_DCN3_0)

	case CHIP_SIENNA_CICHLID:

	case CHIP_NAVY_FLOUNDER:

#endif

#if defined(CONFIG_DRM_AMD_DC_DCN3_02)

	case CHIP_DIMGREY_CAVEFISH:

#endif

#if defined(CONFIG_DRM_AMD_DC_DCN3_01)

	case CHIP_VANGOGH:

#endif

		return 0;

	case CHIP_NAVI12:

		fw_name_dmcu = FIRMWARE_NAVI12_DMCU;
@@ -1320,7 +1308,6 @@ static int dm_dmub_sw_init(struct amdgpu_device *adev) 
		if (ASICREV_IS_GREEN_SARDINE(adev->external_rev_id))

			fw_name_dmub = FIRMWARE_GREEN_SARDINE_DMUB;

		break;

#if defined(CONFIG_DRM_AMD_DC_DCN3_0)

	case CHIP_SIENNA_CICHLID:

		dmub_asic = DMUB_ASIC_DCN30;

		fw_name_dmub = FIRMWARE_SIENNA_CICHLID_DMUB;
@@ -1329,19 +1316,14 @@ static int dm_dmub_sw_init(struct amdgpu_device *adev) 
		dmub_asic = DMUB_ASIC_DCN30;

		fw_name_dmub = FIRMWARE_NAVY_FLOUNDER_DMUB;

		break;

#endif

#if defined(CONFIG_DRM_AMD_DC_DCN3_01)

	case CHIP_VANGOGH:

		dmub_asic = DMUB_ASIC_DCN301;

		fw_name_dmub = FIRMWARE_VANGOGH_DMUB;

		break;

#endif

#if defined(CONFIG_DRM_AMD_DC_DCN3_02)

	case CHIP_DIMGREY_CAVEFISH:

		dmub_asic = DMUB_ASIC_DCN302;

		fw_name_dmub = FIRMWARE_DIMGREY_CAVEFISH_DMUB;

		break;

#endif



	default:

		/* ASIC doesn't support DMUB. */
@@ -3461,16 +3443,10 @@ static int amdgpu_dm_initialize_drm_device(struct amdgpu_device *adev) 
	case CHIP_NAVI10:

	case CHIP_NAVI14:

	case CHIP_RENOIR:

#if defined(CONFIG_DRM_AMD_DC_DCN3_0)

	case CHIP_SIENNA_CICHLID:

	case CHIP_NAVY_FLOUNDER:

#endif

#if defined(CONFIG_DRM_AMD_DC_DCN3_02)

	case CHIP_DIMGREY_CAVEFISH:

#endif

#if defined(CONFIG_DRM_AMD_DC_DCN3_01)

	case CHIP_VANGOGH:

#endif

		if (dcn10_register_irq_handlers(dm->adev)) {

			DRM_ERROR("DM: Failed to initialize IRQ\n");

			goto fail;
@@ -3629,41 +3605,27 @@ static int dm_early_init(void *handle) 
		break;

#if defined(CONFIG_DRM_AMD_DC_DCN)

	case CHIP_RAVEN:

	case CHIP_RENOIR:

	case CHIP_VANGOGH:

		adev->mode_info.num_crtc = 4;

		adev->mode_info.num_hpd = 4;

		adev->mode_info.num_dig = 4;

		break;

#endif

	case CHIP_NAVI10:

	case CHIP_NAVI12:

#if defined(CONFIG_DRM_AMD_DC_DCN3_0)

	case CHIP_SIENNA_CICHLID:

	case CHIP_NAVY_FLOUNDER:

#endif

		adev->mode_info.num_crtc = 6;

		adev->mode_info.num_hpd = 6;

		adev->mode_info.num_dig = 6;

		break;

#if defined(CONFIG_DRM_AMD_DC_DCN3_01)

	case CHIP_VANGOGH:

		adev->mode_info.num_crtc = 4;

		adev->mode_info.num_hpd = 4;

		adev->mode_info.num_dig = 4;

		break;

#endif

	case CHIP_NAVI14:

#if defined(CONFIG_DRM_AMD_DC_DCN3_02)

	case CHIP_DIMGREY_CAVEFISH:

#endif

		adev->mode_info.num_crtc = 5;

		adev->mode_info.num_hpd = 5;

		adev->mode_info.num_dig = 5;

		break;

	case CHIP_RENOIR:

		adev->mode_info.num_crtc = 4;

		adev->mode_info.num_hpd = 4;

		adev->mode_info.num_dig = 4;

		break;

#endif

	default:

		DRM_ERROR("Unsupported ASIC type: 0x%X\n", adev->asic_type);

		return -EINVAL;
@@ -3817,13 +3779,11 @@ fill_gfx9_tiling_info_from_device(const struct amdgpu_device *adev, 
	tiling_info->gfx9.num_rb_per_se =

		adev->gfx.config.gb_addr_config_fields.num_rb_per_se;

	tiling_info->gfx9.shaderEnable = 1;

#ifdef CONFIG_DRM_AMD_DC_DCN3_0

	if (adev->asic_type == CHIP_SIENNA_CICHLID ||

	    adev->asic_type == CHIP_NAVY_FLOUNDER ||

	    adev->asic_type == CHIP_DIMGREY_CAVEFISH ||

	    adev->asic_type == CHIP_VANGOGH)

		tiling_info->gfx9.num_pkrs = adev->gfx.config.gb_addr_config_fields.num_pkrs;

#endif

}



static int

drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_helpers.c

+0 −2
Original line number Diff line number Diff line
@@ -627,7 +627,6 @@ void dm_set_dcn_clocks(struct dc_context *ctx, struct dc_clocks *clks) 
{

	/* TODO: something */

}

#ifdef CONFIG_DRM_AMD_DC_DCN3_0



void *dm_helpers_allocate_gpu_mem(

		struct dc_context *ctx,
@@ -646,4 +645,3 @@ void dm_helpers_free_gpu_mem( 
{

	// TODO

}
 
#endif

drivers/gpu/drm/amd/display/dc/Makefile

+0 −10
Original line number Diff line number Diff line
@@ -30,19 +30,9 @@ DC_LIBS += dcn20 
DC_LIBS += dsc

DC_LIBS += dcn10 dml

DC_LIBS += dcn21

endif



ifdef CONFIG_DRM_AMD_DC_DCN3_0

DC_LIBS += dcn30

endif



ifdef CONFIG_DRM_AMD_DC_DCN3_01

DC_LIBS += dcn301

endif



ifdef CONFIG_DRM_AMD_DC_DCN3_02

DC_LIBS += dcn302



endif



DC_LIBS += dce120

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