Commit 20eea462 authored Mar 25, 2019 by Vandita Kulkarni Committed by Rodrigo Vivi Apr 10, 2019

drm/i915/icl: Ungate ddi clocks before IO enable



IO enable sequencing needs ddi clocks enabled.
These clocks will be gated at a later point in
the enable sequence.

v2: Fix the commit header (Uma)
v3: Remove the redundant read (Ville)

Fixes: 949fc52a ("drm/i915/icl: add pll mapping for DSI")
Signed-off-by: Vandita Kulkarni <vandita.kulkarni@intel.com>
Reviewed-by: Uma Shankar <uma.shankar@intel.com>
Signed-off-by: Jani Nikula <jani.nikula@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/1553513202-13863-1-git-send-email-vandita.kulkarni@intel.com


(cherry picked from commit c5b81a32)
Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>

parent bef42cb2

drivers/gpu/drm/i915/icl_dsi.c

+6 −0

Original line number	Diff line number	Diff line
		@@ -598,6 +598,12 @@ static void gen11_dsi_map_pll(struct intel_encoder *encoder,
		val \|= DPCLKA_CFGCR0_DDI_CLK_SEL(pll->info->id, port);
		}
		I915_WRITE(DPCLKA_CFGCR0_ICL, val);

		for_each_dsi_port(port, intel_dsi->ports) {
		val &= ~DPCLKA_CFGCR0_DDI_CLK_OFF(port);
		}
		I915_WRITE(DPCLKA_CFGCR0_ICL, val);

		POSTING_READ(DPCLKA_CFGCR0_ICL);

		mutex_unlock(&dev_priv->dpll_lock);

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