Commit 20d22927 authored Jan 15, 2020 by Greentime Hu Committed by Paul Walmsley Jan 15, 2020

riscv: make sure the cores stay looping in .Lsecondary_park



The code in secondary_park is currently placed in the .init section. The
kernel reclaims and clears this code when it finishes booting. That
causes the cores parked in it to go to somewhere unpredictable, so we
move this function out of init to make sure the cores stay looping there.

The instruction bgeu a0, t0, .Lsecondary_park may have "a relocation
truncated to fit" issue during linking time. It is because that sections
are too far to jump. Let's use tail to jump to the .Lsecondary_park.

Signed-off-by: Greentime Hu <greentime.hu@sifive.com>
Reviewed-by: Anup Patel <anup.patel@sifive.com>
Cc: Andreas Schwab <schwab@suse.de>
Cc: stable@vger.kernel.org
Fixes: 76d2a049 ("RISC-V: Init and Halt Code")
Signed-off-by: Paul Walmsley <paul.walmsley@sifive.com>

parent b3a987b0

arch/riscv/kernel/head.S

+10 −6

Original line number	Diff line number	Diff line
		@@ -80,7 +80,9 @@ _start_kernel:

		#ifdef CONFIG_SMP
		li t0, CONFIG_NR_CPUS
		bgeu a0, t0, .Lsecondary_park
		blt a0, t0, .Lgood_cores
		tail .Lsecondary_park
		.Lgood_cores:
		#endif

		/* Pick one hart to run the main boot sequence */
		@@ -209,11 +211,6 @@ relocate:
		tail smp_callin
		#endif

		.align 2
		.Lsecondary_park:
		/* We lack SMP support or have too many harts, so park this hart */
		wfi
		j .Lsecondary_park
		END(_start)

		#ifdef CONFIG_RISCV_M_MODE
		@@ -295,6 +292,13 @@ ENTRY(reset_regs)
		END(reset_regs)
		#endif /* CONFIG_RISCV_M_MODE */

		.section ".text", "ax",@progbits
		.align 2
		.Lsecondary_park:
		/* We lack SMP support or have too many harts, so park this hart */
		wfi
		j .Lsecondary_park

		__PAGE_ALIGNED_BSS
		/* Empty zero page */
		.balign PAGE_SIZE

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