Commit 20cc5b64 authored by Thomas Bogendoerfer's avatar Thomas Bogendoerfer
Browse files

MIPS: cpu-probe: remove MIPS_CPU_BP_GHIST option bit 



MIPS_CPU_BP_GHIST is only set two times and more or less immediately
used in cpu-probe.c itself. Remove this option to make room in options
word.

Signed-off-by: default avatarThomas Bogendoerfer <tsbogend@alpha.franken.de>
parent 90c68c6d

arch/mips/include/asm/cpu-features.h

+0 −3
Original line number Diff line number Diff line
@@ -171,9 +171,6 @@ 
#ifndef cpu_has_llsc

#define cpu_has_llsc		__isa_ge_or_opt(1, MIPS_CPU_LLSC)

#endif

#ifndef cpu_has_bp_ghist

#define cpu_has_bp_ghist	__opt(MIPS_CPU_BP_GHIST)

#endif

#ifndef kernel_uses_llsc

#define kernel_uses_llsc	cpu_has_llsc

#endif

arch/mips/include/asm/cpu.h

+0 −1
Original line number Diff line number Diff line
@@ -398,7 +398,6 @@ enum cpu_type_enum { 
#define MIPS_CPU_RW_LLB		BIT_ULL(32)	/* LLADDR/LLB writes are allowed */

#define MIPS_CPU_LPA		BIT_ULL(33)	/* CPU supports Large Physical Addressing */

#define MIPS_CPU_CDMM		BIT_ULL(34)	/* CPU has Common Device Memory Map */

#define MIPS_CPU_BP_GHIST	BIT_ULL(35)	/* R12K+ Branch Prediction Global History */

#define MIPS_CPU_SP		BIT_ULL(36)	/* Small (1KB) page support */

#define MIPS_CPU_FTLB		BIT_ULL(37)	/* CPU has Fixed-page-size TLB */

#define MIPS_CPU_NAN_LEGACY	BIT_ULL(38)	/* Legacy NaN implemented */

arch/mips/include/asm/mach-au1x00/cpu-feature-overrides.h

+0 −1
Original line number Diff line number Diff line
@@ -39,7 +39,6 @@ 
#define cpu_has_guestctl2		0

#define cpu_has_guestid			0

#define cpu_has_drg			0

#define cpu_has_bp_ghist		0

#define cpu_has_mips16			0

#define cpu_has_mips16e2		0

#define cpu_has_mdmx			0

arch/mips/kernel/cpu-probe.c

+4 −6
Original line number Diff line number Diff line
@@ -1278,8 +1278,9 @@ static inline void cpu_probe_legacy(struct cpuinfo_mips *c, unsigned int cpu) 
		c->options = MIPS_CPU_TLB | MIPS_CPU_4K_CACHE | MIPS_CPU_4KEX |

			     MIPS_CPU_FPU | MIPS_CPU_32FPR |

			     MIPS_CPU_COUNTER | MIPS_CPU_WATCH |

			     MIPS_CPU_LLSC | MIPS_CPU_BP_GHIST;

			     MIPS_CPU_LLSC;

		c->tlbsize = 64;

		write_c0_r10k_diag(read_c0_r10k_diag() | R10K_DIAG_E_GHIST);

		break;

	case PRID_IMP_R14000:

		if (((c->processor_id >> 4) & 0x0f) > 2) {
@@ -1293,8 +1294,9 @@ static inline void cpu_probe_legacy(struct cpuinfo_mips *c, unsigned int cpu) 
		c->options = MIPS_CPU_TLB | MIPS_CPU_4K_CACHE | MIPS_CPU_4KEX |

			     MIPS_CPU_FPU | MIPS_CPU_32FPR |

			     MIPS_CPU_COUNTER | MIPS_CPU_WATCH |

			     MIPS_CPU_LLSC | MIPS_CPU_BP_GHIST;

			     MIPS_CPU_LLSC;

		c->tlbsize = 64;

		write_c0_r10k_diag(read_c0_r10k_diag() | R10K_DIAG_E_GHIST);

		break;

	case PRID_IMP_LOONGSON_64C:  /* Loongson-2/3 */

		switch (c->processor_id & PRID_REV_MASK) {
@@ -2054,10 +2056,6 @@ void cpu_probe(void) 
	else

		cpu_set_nofpu_opts(c);



	if (cpu_has_bp_ghist)

		write_c0_r10k_diag(read_c0_r10k_diag() |

				   R10K_DIAG_E_GHIST);



	if (cpu_has_mips_r2_r6) {

		c->srsets = ((read_c0_srsctl() >> 26) & 0x0f) + 1;

		/* R2 has Performance Counter Interrupt indicator */

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