Commit 20bde643 authored Dec 17, 2015 by Yunzhi Li Committed by Felipe Balbi Dec 22, 2015

usb: dwc2: reduce dwc2 driver probe time



I found that the probe function of dwc2 driver takes much time
when kernel boot up. There are many long delays in the probe
function these take almost 1 second.

This patch trying to reduce unnecessary delay time.

In dwc2_core_reset() I see it use two at least 20ms delays to
wait AHB idle and core soft reset, but dwc2 data book said that
dwc2 core soft reset and AHB idle just need a few clocks (I think
it refers to AHB clock, and AHB clock run at 150MHz in my RK3288
board), so 20ms is too long, delay 1us for wait AHB idle and soft
reset is enough.

And in dwc2_get_hwparams() it takes 150ms to wait ForceHostMode
and ForceDeviceMode valid but in data book it said software must
wait at least 25ms before the change to take effect, so I reduce
this time to 25ms~50ms. By the way, is there any state bit show
that the force mode take effect ? Could we poll curmod bit for
figuring out if the change take effect ?

It seems that usleep_range() at boot time will pick the longest
value in the range. In dwc2_core_reset() there is a very long
delay takes 200ms, and this function run twice when probe, could
any one tell me is this delay time resonable ?

I have tried this patch in my RK3288-evb board. It works well.

Signed-off-by: Yunzhi Li <lyz@rock-chips.com>
Signed-off-by: Douglas Anderson <dianders@chromium.org>
Signed-off-by: John Youn <johnyoun@synopsys.com>
Signed-off-by: Felipe Balbi <balbi@ti.com>

parent f6194731

drivers/usb/dwc2/core.c

+5 −5

Original line number	Diff line number	Diff line
		@@ -491,7 +491,7 @@ int dwc2_core_reset(struct dwc2_hsotg *hsotg)

		/* Wait for AHB master IDLE state */
		do {
		usleep_range(20000, 40000);
		udelay(1);
		greset = dwc2_readl(hsotg->regs + GRSTCTL);
		if (++count > 50) {
		dev_warn(hsotg->dev,
		@@ -506,7 +506,7 @@ int dwc2_core_reset(struct dwc2_hsotg *hsotg)
		greset \|= GRSTCTL_CSFTRST;
		dwc2_writel(greset, hsotg->regs + GRSTCTL);
		do {
		usleep_range(20000, 40000);
		udelay(1);
		greset = dwc2_readl(hsotg->regs + GRSTCTL);
		if (++count > 50) {
		dev_warn(hsotg->dev,
		@@ -537,7 +537,7 @@ int dwc2_core_reset(struct dwc2_hsotg *hsotg)
		* NOTE: This long sleep is _very_ important, otherwise the core will
		* not stay in host mode after a connector ID change!
		*/
		usleep_range(150000, 200000);
		usleep_range(150000, 160000);

		return 0;
		}
		@@ -3139,7 +3139,7 @@ int dwc2_get_hwparams(struct dwc2_hsotg *hsotg)
		gusbcfg = dwc2_readl(hsotg->regs + GUSBCFG);
		dwc2_writel(gusbcfg \| GUSBCFG_FORCEHOSTMODE,
		hsotg->regs + GUSBCFG);
		usleep_range(100000, 150000);
		usleep_range(25000, 50000);
		}

		gnptxfsiz = dwc2_readl(hsotg->regs + GNPTXFSIZ);
		@@ -3148,7 +3148,7 @@ int dwc2_get_hwparams(struct dwc2_hsotg *hsotg)
		dev_dbg(hsotg->dev, "hptxfsiz=%08x\n", hptxfsiz);
		if (hsotg->dr_mode != USB_DR_MODE_HOST) {
		dwc2_writel(gusbcfg, hsotg->regs + GUSBCFG);
		usleep_range(100000, 150000);
		usleep_range(25000, 50000);
		}

		/* hwcfg2 */

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