Commit 209d7353 authored by Imre Deak's avatar Imre Deak
Browse files

drm/i915/icl: Prevent incorrect DBuf enabling 

Pretend that we have only 1 DBuf slice and that 1 slice is always
enabled, until we have a proper way for on-demand toggling of the second
slice.  Currently we'll try to incorrectly enable DBuf even when all
pipes are disabled and we are already runtime suspended (as the computed
number of DBuf slices will be 1 in that case).

This also means we'll leave the second slice enabled redundantly (except
when suspended), but that's an acceptable tradeoff until we have a
proper solution.

Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=108756


Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
Signed-off-by: default avatarImre Deak <imre.deak@intel.com>
Reviewed-by: default avatarRodrigo Vivi <rodrigo.vivi@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20190307103235.23538-1-imre.deak@intel.com
parent 2835f4f3

drivers/gpu/drm/i915/intel_pm.c

+6 −1
Original line number Original line Diff line number Diff line
@@ -3624,7 +3624,12 @@ static u8 intel_enabled_dbuf_slices_num(struct drm_i915_private *dev_priv) 
	if (INTEL_GEN(dev_priv) < 11)

	if (INTEL_GEN(dev_priv) < 11)

		return enabled_slices;

		return enabled_slices;





	if (I915_READ(DBUF_CTL_S2) & DBUF_POWER_STATE)

	/*

	 * FIXME: for now we'll only ever use 1 slice; pretend that we have

	 * only that 1 slice enabled until we have a proper way for on-demand

	 * toggling of the second slice.

	 */

	if (0 && I915_READ(DBUF_CTL_S2) & DBUF_POWER_STATE)

		enabled_slices++;

		enabled_slices++;





	return enabled_slices;

	return enabled_slices;

drivers/gpu/drm/i915/intel_runtime_pm.c

+10 −2
Original line number Original line Diff line number Diff line
@@ -3576,7 +3576,11 @@ static void icl_dbuf_enable(struct drm_i915_private *dev_priv) 
	    !(I915_READ(DBUF_CTL_S2) & DBUF_POWER_STATE))

	    !(I915_READ(DBUF_CTL_S2) & DBUF_POWER_STATE))

		DRM_ERROR("DBuf power enable timeout\n");

		DRM_ERROR("DBuf power enable timeout\n");

	else

	else

		dev_priv->wm.skl_hw.ddb.enabled_slices = 2;

		/*

		 * FIXME: for now pretend that we only have 1 slice, see

		 * intel_enabled_dbuf_slices_num().

		 */

		dev_priv->wm.skl_hw.ddb.enabled_slices = 1;

}

}





static void icl_dbuf_disable(struct drm_i915_private *dev_priv)

static void icl_dbuf_disable(struct drm_i915_private *dev_priv)
@@ -3591,7 +3595,11 @@ static void icl_dbuf_disable(struct drm_i915_private *dev_priv) 
	    (I915_READ(DBUF_CTL_S2) & DBUF_POWER_STATE))

	    (I915_READ(DBUF_CTL_S2) & DBUF_POWER_STATE))

		DRM_ERROR("DBuf power disable timeout!\n");

		DRM_ERROR("DBuf power disable timeout!\n");

	else

	else

		dev_priv->wm.skl_hw.ddb.enabled_slices = 0;

		/*

		 * FIXME: for now pretend that the first slice is always

		 * enabled, see intel_enabled_dbuf_slices_num().

		 */

		dev_priv->wm.skl_hw.ddb.enabled_slices = 1;

}

}





static void icl_mbus_init(struct drm_i915_private *dev_priv)

static void icl_mbus_init(struct drm_i915_private *dev_priv)

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