Commit 204ce75b authored by Dmitry Osipenko's avatar Dmitry Osipenko Committed by Thierry Reding
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clk: tegra: Optimize PLLX restore on Tegra20/30 



There is no need to re-configure PLLX if its configuration in unchanged
on return from suspend / cpuidle, this saves 300us if PLLX is already
enabled (common case for cpuidle).

Signed-off-by: default avatarDmitry Osipenko <digetx@gmail.com>
Acked-by: default avatarPeter De Schrijver <pdeschrijver@nvidia.com>
Signed-off-by: default avatarThierry Reding <treding@nvidia.com>
parent 535f296d

drivers/clk/tegra/clk-tegra20.c

+16 −9
Original line number Diff line number Diff line
@@ -955,6 +955,7 @@ static void tegra20_cpu_clock_suspend(void) 
static void tegra20_cpu_clock_resume(void)

{

	unsigned int reg, policy;

	u32 misc, base;



	/* Is CPU complex already running on PLLX? */

	reg = readl(clk_base + CCLK_BURST_POLICY);
@@ -968,6 +969,11 @@ static void tegra20_cpu_clock_resume(void) 
		BUG();



	if (reg != CCLK_BURST_POLICY_PLLX) {

		misc = readl_relaxed(clk_base + PLLX_MISC);

		base = readl_relaxed(clk_base + PLLX_BASE);



		if (misc != tegra20_cpu_clk_sctx.pllx_misc ||

		    base != tegra20_cpu_clk_sctx.pllx_base) {

			/* restore PLLX settings if CPU is on different PLL */

			writel(tegra20_cpu_clk_sctx.pllx_misc,

						clk_base + PLLX_MISC);
@@ -978,6 +984,7 @@ static void tegra20_cpu_clock_resume(void) 
			if (tegra20_cpu_clk_sctx.pllx_base & (1 << 30))

				udelay(300);

		}

	}



	/*

	 * Restore original burst policy setting for calls resulting from CPU

drivers/clk/tegra/clk-tegra30.c

+16 −9
Original line number Diff line number Diff line
@@ -1163,6 +1163,7 @@ static void tegra30_cpu_clock_suspend(void) 
static void tegra30_cpu_clock_resume(void)

{

	unsigned int reg, policy;

	u32 misc, base;



	/* Is CPU complex already running on PLLX? */

	reg = readl(clk_base + CLK_RESET_CCLK_BURST);
@@ -1176,6 +1177,11 @@ static void tegra30_cpu_clock_resume(void) 
		BUG();



	if (reg != CLK_RESET_CCLK_BURST_POLICY_PLLX) {

		misc = readl_relaxed(clk_base + CLK_RESET_PLLX_MISC);

		base = readl_relaxed(clk_base + CLK_RESET_PLLX_BASE);



		if (misc != tegra30_cpu_clk_sctx.pllx_misc ||

		    base != tegra30_cpu_clk_sctx.pllx_base) {

			/* restore PLLX settings if CPU is on different PLL */

			writel(tegra30_cpu_clk_sctx.pllx_misc,

						clk_base + CLK_RESET_PLLX_MISC);
@@ -1186,6 +1192,7 @@ static void tegra30_cpu_clock_resume(void) 
			if (tegra30_cpu_clk_sctx.pllx_base & (1 << 30))

				udelay(300);

		}

	}



	/*

	 * Restore original burst policy setting for calls resulting from CPU

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