ARM: 5888/1: arm: Update comments in cacheflush.h and remove unnecessary V6 and V7 comments (2045124f) · Commits · 戴 / test

arch/arm/include/asm/cacheflush.h

+17 −3

Original line number	Diff line number	Diff line
		@@ -154,16 +154,16 @@
		* Please note that the implementation of these, and the required
		* effects are cache-type (VIVT/VIPT/PIPT) specific.
		*
		* flush_cache_kern_all()
		* flush_kern_all()
		*
		* Unconditionally clean and invalidate the entire cache.
		*
		* flush_cache_user_mm(mm)
		* flush_user_all()
		*
		* Clean and invalidate all user space cache entries
		* before a change of page tables.
		*
		* flush_cache_user_range(start, end, flags)
		* flush_user_range(start, end, flags)
		*
		* Clean and invalidate a range of cache entries in the
		* specified address space before a change of page tables.
		@@ -179,6 +179,20 @@
		* - start - virtual start address
		* - end - virtual end address
		*
		* coherent_user_range(start, end)
		*
		* Ensure coherency between the Icache and the Dcache in the
		* region described by start, end. If you have non-snooping
		* Harvard caches, you need to implement this function.
		* - start - virtual start address
		* - end - virtual end address
		*
		* flush_kern_dcache_area(kaddr, size)
		*
		* Ensure that the data held in page is written back.
		* - kaddr - page address
		* - size - region size
		*
		* DMA Cache Coherency
		* ===================
		*

+0 −2

Original line number	Diff line number	Diff line
		@@ -59,8 +59,6 @@ ENTRY(cpu_v6_proc_fin)
		* to what would be the reset vector.
		*
		* - loc - location to jump to for soft reset
		*
		* It is assumed that:
		*/
		.align 5
		ENTRY(cpu_v6_reset)

+0 −2

Original line number	Diff line number	Diff line
		@@ -63,8 +63,6 @@ ENDPROC(cpu_v7_proc_fin)
		* to what would be the reset vector.
		*
		* - loc - location to jump to for soft reset
		*
		* It is assumed that:
		*/
		.align 5
		ENTRY(cpu_v7_reset)