Commit 2002bc32 authored by David S. Miller's avatar David S. Miller
Browse files

Merge branch 'dsa-b53-SerDes-support' 



Florian Fainelli says:

====================
net: dsa: b53: SerDes support

This patch series adds support for the SerDes found on NorthStar Plus
(NSP) which allows us to use the SFP port on the BCM958625HR board (and
other similar designs).

Changes in v3:

- properly hunk the request_threaded_irq() bits into patch #2

Changes in v2:

- migrate to threaded interrupt (Andrew)
- fixed a case where MLO_AN_FIXED's mac_config would still call into
  the serdes_config callback
- added an additional check on the phylink interface in mac_config
- default to ARCH_BCM_NSP instead of ARCH_BCM_IPROC which is really
  the NSP Kconfig bit we want
====================

Signed-off-by: default avatarDavid S. Miller <davem@davemloft.net>
parents a3f72307 0e01491d

drivers/net/dsa/b53/Kconfig

+7 −0
Original line number Diff line number Diff line
@@ -35,3 +35,10 @@ config B53_SRAB_DRIVER 
	help

	  Select to enable support for memory-mapped Switch Register Access

	  Bridge Registers (SRAB) like it is found on the BCM53010



config B53_SERDES

	tristate "B53 SerDes support"

	depends on B53

	default ARCH_BCM_NSP

	help

	  Select to enable support for SerDes on e.g: Northstar Plus SoCs.

drivers/net/dsa/b53/Makefile

+1 −0
Original line number Diff line number Diff line
@@ -5,3 +5,4 @@ obj-$(CONFIG_B53_SPI_DRIVER) += b53_spi.o 
obj-$(CONFIG_B53_MDIO_DRIVER)	+= b53_mdio.o

obj-$(CONFIG_B53_MMAP_DRIVER)	+= b53_mmap.o

obj-$(CONFIG_B53_SRAB_DRIVER)	+= b53_srab.o

obj-$(CONFIG_B53_SERDES)	+= b53_serdes.o

drivers/net/dsa/b53/b53_common.c

+217 −29
Original line number Diff line number Diff line
@@ -26,6 +26,7 @@ 
#include <linux/module.h>

#include <linux/platform_data/b53.h>

#include <linux/phy.h>

#include <linux/phylink.h>

#include <linux/etherdevice.h>

#include <linux/if_bridge.h>

#include <net/dsa.h>
@@ -502,8 +503,14 @@ int b53_enable_port(struct dsa_switch *ds, int port, struct phy_device *phy) 
{

	struct b53_device *dev = ds->priv;

	unsigned int cpu_port = ds->ports[port].cpu_dp->index;

	int ret = 0;

	u16 pvlan;



	if (dev->ops->irq_enable)

		ret = dev->ops->irq_enable(dev, port);

	if (ret)

		return ret;



	/* Clear the Rx and Tx disable bits and set to no spanning tree */

	b53_write8(dev, B53_CTRL_PAGE, B53_PORT_CTRL(port), 0);
@@ -536,6 +543,9 @@ void b53_disable_port(struct dsa_switch *ds, int port, struct phy_device *phy) 
	b53_read8(dev, B53_CTRL_PAGE, B53_PORT_CTRL(port), &reg);

	reg |= PORT_CTRL_RX_DISABLE | PORT_CTRL_TX_DISABLE;

	b53_write8(dev, B53_CTRL_PAGE, B53_PORT_CTRL(port), reg);



	if (dev->ops->irq_disable)

		dev->ops->irq_disable(dev, port);

}

EXPORT_SYMBOL(b53_disable_port);
@@ -755,6 +765,8 @@ static int b53_reset_switch(struct b53_device *priv) 
	memset(priv->vlans, 0, sizeof(*priv->vlans) * priv->num_vlans);

	memset(priv->ports, 0, sizeof(*priv->ports) * priv->num_ports);



	priv->serdes_lane = B53_INVALID_LANE;



	return b53_switch_reset(priv);

}
@@ -938,33 +950,50 @@ static int b53_setup(struct dsa_switch *ds) 
	return ret;

}



static void b53_adjust_link(struct dsa_switch *ds, int port,

			    struct phy_device *phydev)

static void b53_force_link(struct b53_device *dev, int port, int link)

{

	struct b53_device *dev = ds->priv;

	struct ethtool_eee *p = &dev->ports[port].eee;

	u8 rgmii_ctrl = 0, reg = 0, off;



	if (!phy_is_pseudo_fixed_link(phydev))

		return;

	u8 reg, val, off;



	/* Override the port settings */

	if (port == dev->cpu_port) {

		off = B53_PORT_OVERRIDE_CTRL;

		reg = PORT_OVERRIDE_EN;

		val = PORT_OVERRIDE_EN;

	} else {

		off = B53_GMII_PORT_OVERRIDE_CTRL(port);

		reg = GMII_PO_EN;

		val = GMII_PO_EN;

	}



	/* Set the link UP */

	if (phydev->link)

	b53_read8(dev, B53_CTRL_PAGE, off, &reg);

	reg |= val;

	if (link)

		reg |= PORT_OVERRIDE_LINK;

	else

		reg &= ~PORT_OVERRIDE_LINK;

	b53_write8(dev, B53_CTRL_PAGE, off, reg);

}



static void b53_force_port_config(struct b53_device *dev, int port,

				  int speed, int duplex, int pause)

{

	u8 reg, val, off;



	if (phydev->duplex == DUPLEX_FULL)

	/* Override the port settings */

	if (port == dev->cpu_port) {

		off = B53_PORT_OVERRIDE_CTRL;

		val = PORT_OVERRIDE_EN;

	} else {

		off = B53_GMII_PORT_OVERRIDE_CTRL(port);

		val = GMII_PO_EN;

	}



	b53_read8(dev, B53_CTRL_PAGE, off, &reg);

	reg |= val;

	if (duplex == DUPLEX_FULL)

		reg |= PORT_OVERRIDE_FULL_DUPLEX;

	else

		reg &= ~PORT_OVERRIDE_FULL_DUPLEX;



	switch (phydev->speed) {

	switch (speed) {

	case 2000:

		reg |= PORT_OVERRIDE_SPEED_2000M;

		/* fallthrough */
@@ -978,21 +1007,41 @@ static void b53_adjust_link(struct dsa_switch *ds, int port, 
		reg |= PORT_OVERRIDE_SPEED_10M;

		break;

	default:

		dev_err(ds->dev, "unknown speed: %d\n", phydev->speed);

		dev_err(dev->dev, "unknown speed: %d\n", speed);

		return;

	}



	if (pause & MLO_PAUSE_RX)

		reg |= PORT_OVERRIDE_RX_FLOW;

	if (pause & MLO_PAUSE_TX)

		reg |= PORT_OVERRIDE_TX_FLOW;



	b53_write8(dev, B53_CTRL_PAGE, off, reg);

}



static void b53_adjust_link(struct dsa_switch *ds, int port,

			    struct phy_device *phydev)

{

	struct b53_device *dev = ds->priv;

	struct ethtool_eee *p = &dev->ports[port].eee;

	u8 rgmii_ctrl = 0, reg = 0, off;

	int pause;



	if (!phy_is_pseudo_fixed_link(phydev))

		return;



	/* Enable flow control on BCM5301x's CPU port */

	if (is5301x(dev) && port == dev->cpu_port)

		reg |= PORT_OVERRIDE_RX_FLOW | PORT_OVERRIDE_TX_FLOW;

		pause = MLO_PAUSE_TXRX_MASK;



	if (phydev->pause) {

		if (phydev->asym_pause)

			reg |= PORT_OVERRIDE_TX_FLOW;

		reg |= PORT_OVERRIDE_RX_FLOW;

			pause |= MLO_PAUSE_TX;

		pause |= MLO_PAUSE_RX;

	}



	b53_write8(dev, B53_CTRL_PAGE, off, reg);

	b53_force_port_config(dev, port, phydev->speed, phydev->duplex, pause);

	b53_force_link(dev, port, phydev->link);



	if (is531x5(dev) && phy_interface_is_rgmii(phydev)) {

		if (port == 8)
@@ -1052,16 +1101,9 @@ static void b53_adjust_link(struct dsa_switch *ds, int port, 
		}

	} else if (is5301x(dev)) {

		if (port != dev->cpu_port) {

			u8 po_reg = B53_GMII_PORT_OVERRIDE_CTRL(dev->cpu_port);

			u8 gmii_po;



			b53_read8(dev, B53_CTRL_PAGE, po_reg, &gmii_po);

			gmii_po |= GMII_PO_LINK |

				   GMII_PO_RX_FLOW |

				   GMII_PO_TX_FLOW |

				   GMII_PO_EN |

				   GMII_PO_SPEED_2000M;

			b53_write8(dev, B53_CTRL_PAGE, po_reg, gmii_po);

			b53_force_port_config(dev, dev->cpu_port, 2000,

					      DUPLEX_FULL, MLO_PAUSE_TXRX_MASK);

			b53_force_link(dev, dev->cpu_port, 1);

		}

	}
@@ -1069,6 +1111,146 @@ static void b53_adjust_link(struct dsa_switch *ds, int port, 
	p->eee_enabled = b53_eee_init(ds, port, phydev);

}



void b53_port_event(struct dsa_switch *ds, int port)

{

	struct b53_device *dev = ds->priv;

	bool link;

	u16 sts;



	b53_read16(dev, B53_STAT_PAGE, B53_LINK_STAT, &sts);

	link = !!(sts & BIT(port));

	dsa_port_phylink_mac_change(ds, port, link);

}

EXPORT_SYMBOL(b53_port_event);



void b53_phylink_validate(struct dsa_switch *ds, int port,

			  unsigned long *supported,

			  struct phylink_link_state *state)

{

	struct b53_device *dev = ds->priv;

	__ETHTOOL_DECLARE_LINK_MODE_MASK(mask) = { 0, };



	if (dev->ops->serdes_phylink_validate)

		dev->ops->serdes_phylink_validate(dev, port, mask, state);



	/* Allow all the expected bits */

	phylink_set(mask, Autoneg);

	phylink_set_port_modes(mask);

	phylink_set(mask, Pause);

	phylink_set(mask, Asym_Pause);



	/* With the exclusion of 5325/5365, MII, Reverse MII and 802.3z, we

	 * support Gigabit, including Half duplex.

	 */

	if (state->interface != PHY_INTERFACE_MODE_MII &&

	    state->interface != PHY_INTERFACE_MODE_REVMII &&

	    !phy_interface_mode_is_8023z(state->interface) &&

	    !(is5325(dev) || is5365(dev))) {

		phylink_set(mask, 1000baseT_Full);

		phylink_set(mask, 1000baseT_Half);

	}



	if (!phy_interface_mode_is_8023z(state->interface)) {

		phylink_set(mask, 10baseT_Half);

		phylink_set(mask, 10baseT_Full);

		phylink_set(mask, 100baseT_Half);

		phylink_set(mask, 100baseT_Full);

	}



	bitmap_and(supported, supported, mask,

		   __ETHTOOL_LINK_MODE_MASK_NBITS);

	bitmap_and(state->advertising, state->advertising, mask,

		   __ETHTOOL_LINK_MODE_MASK_NBITS);



	phylink_helper_basex_speed(state);

}

EXPORT_SYMBOL(b53_phylink_validate);



int b53_phylink_mac_link_state(struct dsa_switch *ds, int port,

			       struct phylink_link_state *state)

{

	struct b53_device *dev = ds->priv;

	int ret = -EOPNOTSUPP;



	if (phy_interface_mode_is_8023z(state->interface) &&

	    dev->ops->serdes_link_state)

		ret = dev->ops->serdes_link_state(dev, port, state);



	return ret;

}

EXPORT_SYMBOL(b53_phylink_mac_link_state);



void b53_phylink_mac_config(struct dsa_switch *ds, int port,

			    unsigned int mode,

			    const struct phylink_link_state *state)

{

	struct b53_device *dev = ds->priv;



	if (mode == MLO_AN_PHY)

		return;



	if (mode == MLO_AN_FIXED) {

		b53_force_port_config(dev, port, state->speed,

				      state->duplex, state->pause);

		return;

	}



	if (phy_interface_mode_is_8023z(state->interface) &&

	    dev->ops->serdes_config)

		dev->ops->serdes_config(dev, port, mode, state);

}

EXPORT_SYMBOL(b53_phylink_mac_config);



void b53_phylink_mac_an_restart(struct dsa_switch *ds, int port)

{

	struct b53_device *dev = ds->priv;



	if (dev->ops->serdes_an_restart)

		dev->ops->serdes_an_restart(dev, port);

}

EXPORT_SYMBOL(b53_phylink_mac_an_restart);



void b53_phylink_mac_link_down(struct dsa_switch *ds, int port,

			       unsigned int mode,

			       phy_interface_t interface)

{

	struct b53_device *dev = ds->priv;



	if (mode == MLO_AN_PHY)

		return;



	if (mode == MLO_AN_FIXED) {

		b53_force_link(dev, port, false);

		return;

	}



	if (phy_interface_mode_is_8023z(interface) &&

	    dev->ops->serdes_link_set)

		dev->ops->serdes_link_set(dev, port, mode, interface, false);

}

EXPORT_SYMBOL(b53_phylink_mac_link_down);



void b53_phylink_mac_link_up(struct dsa_switch *ds, int port,

			     unsigned int mode,

			     phy_interface_t interface,

			     struct phy_device *phydev)

{

	struct b53_device *dev = ds->priv;



	if (mode == MLO_AN_PHY)

		return;



	if (mode == MLO_AN_FIXED) {

		b53_force_link(dev, port, true);

		return;

	}



	if (phy_interface_mode_is_8023z(interface) &&

	    dev->ops->serdes_link_set)

		dev->ops->serdes_link_set(dev, port, mode, interface, true);

}

EXPORT_SYMBOL(b53_phylink_mac_link_up);



int b53_vlan_filtering(struct dsa_switch *ds, int port, bool vlan_filtering)

{

	return 0;
@@ -1710,6 +1892,12 @@ static const struct dsa_switch_ops b53_switch_ops = { 
	.phy_read		= b53_phy_read16,

	.phy_write		= b53_phy_write16,

	.adjust_link		= b53_adjust_link,

	.phylink_validate	= b53_phylink_validate,

	.phylink_mac_link_state	= b53_phylink_mac_link_state,

	.phylink_mac_config	= b53_phylink_mac_config,

	.phylink_mac_an_restart	= b53_phylink_mac_an_restart,

	.phylink_mac_link_down	= b53_phylink_mac_link_down,

	.phylink_mac_link_up	= b53_phylink_mac_link_up,

	.port_enable		= b53_enable_port,

	.port_disable		= b53_disable_port,

	.get_mac_eee		= b53_get_mac_eee,

drivers/net/dsa/b53/b53_priv.h

+36 −0
Original line number Diff line number Diff line
@@ -29,6 +29,7 @@ 


struct b53_device;

struct net_device;

struct phylink_link_state;



struct b53_io_ops {

	int (*read8)(struct b53_device *dev, u8 page, u8 reg, u8 *value);
@@ -43,8 +44,25 @@ struct b53_io_ops { 
	int (*write64)(struct b53_device *dev, u8 page, u8 reg, u64 value);

	int (*phy_read16)(struct b53_device *dev, int addr, int reg, u16 *value);

	int (*phy_write16)(struct b53_device *dev, int addr, int reg, u16 value);

	int (*irq_enable)(struct b53_device *dev, int port);

	void (*irq_disable)(struct b53_device *dev, int port);

	u8 (*serdes_map_lane)(struct b53_device *dev, int port);

	int (*serdes_link_state)(struct b53_device *dev, int port,

				 struct phylink_link_state *state);

	void (*serdes_config)(struct b53_device *dev, int port,

			      unsigned int mode,

			      const struct phylink_link_state *state);

	void (*serdes_an_restart)(struct b53_device *dev, int port);

	void (*serdes_link_set)(struct b53_device *dev, int port,

				unsigned int mode, phy_interface_t interface,

				bool link_up);

	void (*serdes_phylink_validate)(struct b53_device *dev, int port,

					unsigned long *supported,

					struct phylink_link_state *state);

};



#define B53_INVALID_LANE	0xff



enum {

	BCM5325_DEVICE_ID = 0x25,

	BCM5365_DEVICE_ID = 0x65,
@@ -107,6 +125,7 @@ struct b53_device { 
	/* connect specific data */

	u8 current_page;

	struct device *dev;

	u8 serdes_lane;



	/* Master MDIO bus we got probed from */

	struct mii_bus *bus;
@@ -298,6 +317,23 @@ int b53_br_join(struct dsa_switch *ds, int port, struct net_device *bridge); 
void b53_br_leave(struct dsa_switch *ds, int port, struct net_device *bridge);

void b53_br_set_stp_state(struct dsa_switch *ds, int port, u8 state);

void b53_br_fast_age(struct dsa_switch *ds, int port);

void b53_port_event(struct dsa_switch *ds, int port);

void b53_phylink_validate(struct dsa_switch *ds, int port,

			  unsigned long *supported,

			  struct phylink_link_state *state);

int b53_phylink_mac_link_state(struct dsa_switch *ds, int port,

			       struct phylink_link_state *state);

void b53_phylink_mac_config(struct dsa_switch *ds, int port,

			    unsigned int mode,

			    const struct phylink_link_state *state);

void b53_phylink_mac_an_restart(struct dsa_switch *ds, int port);

void b53_phylink_mac_link_down(struct dsa_switch *ds, int port,

			       unsigned int mode,

			       phy_interface_t interface);

void b53_phylink_mac_link_up(struct dsa_switch *ds, int port,

			     unsigned int mode,

			     phy_interface_t interface,

			     struct phy_device *phydev);

int b53_vlan_filtering(struct dsa_switch *ds, int port, bool vlan_filtering);

int b53_vlan_prepare(struct dsa_switch *ds, int port,

		     const struct switchdev_obj_port_vlan *vlan);

drivers/net/dsa/b53/b53_serdes.c

0 → 100644
+217 −0
Original line number Diff line number Diff line 
// SPDX-License-Identifier: GPL-2.0 or BSD-3-Clause

/*

 * Northstar Plus switch SerDes/SGMII PHY main logic

 *

 * Copyright (C) 2018 Florian Fainelli <f.fainelli@gmail.com>

 */



#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt



#include <linux/delay.h>

#include <linux/kernel.h>

#include <linux/phy.h>

#include <linux/phylink.h>

#include <net/dsa.h>



#include "b53_priv.h"

#include "b53_serdes.h"

#include "b53_regs.h"



static void b53_serdes_write_blk(struct b53_device *dev, u8 offset, u16 block,

				 u16 value)

{

	b53_write16(dev, B53_SERDES_PAGE, B53_SERDES_BLKADDR, block);

	b53_write16(dev, B53_SERDES_PAGE, offset, value);

}



static u16 b53_serdes_read_blk(struct b53_device *dev, u8 offset, u16 block)

{

	u16 value;



	b53_write16(dev, B53_SERDES_PAGE, B53_SERDES_BLKADDR, block);

	b53_read16(dev, B53_SERDES_PAGE, offset, &value);



	return value;

}



static void b53_serdes_set_lane(struct b53_device *dev, u8 lane)

{

	if (dev->serdes_lane == lane)

		return;



	WARN_ON(lane > 1);



	b53_serdes_write_blk(dev, B53_SERDES_LANE,

			     SERDES_XGXSBLK0_BLOCKADDRESS, lane);

	dev->serdes_lane = lane;

}



static void b53_serdes_write(struct b53_device *dev, u8 lane,

			     u8 offset, u16 block, u16 value)

{

	b53_serdes_set_lane(dev, lane);

	b53_serdes_write_blk(dev, offset, block, value);

}



static u16 b53_serdes_read(struct b53_device *dev, u8 lane,

			   u8 offset, u16 block)

{

	b53_serdes_set_lane(dev, lane);

	return b53_serdes_read_blk(dev, offset, block);

}



void b53_serdes_config(struct b53_device *dev, int port, unsigned int mode,

		       const struct phylink_link_state *state)

{

	u8 lane = b53_serdes_map_lane(dev, port);

	u16 reg;



	if (lane == B53_INVALID_LANE)

		return;



	reg = b53_serdes_read(dev, lane, B53_SERDES_DIGITAL_CONTROL(1),

			      SERDES_DIGITAL_BLK);

	if (state->interface == PHY_INTERFACE_MODE_1000BASEX)

		reg |= FIBER_MODE_1000X;

	else

		reg &= ~FIBER_MODE_1000X;

	b53_serdes_write(dev, lane, B53_SERDES_DIGITAL_CONTROL(1),

			 SERDES_DIGITAL_BLK, reg);

}

EXPORT_SYMBOL(b53_serdes_config);



void b53_serdes_an_restart(struct b53_device *dev, int port)

{

	u8 lane = b53_serdes_map_lane(dev, port);

	u16 reg;



	if (lane == B53_INVALID_LANE)

		return;



	reg = b53_serdes_read(dev, lane, B53_SERDES_MII_REG(MII_BMCR),

			      SERDES_MII_BLK);

	reg |= BMCR_ANRESTART;

	b53_serdes_write(dev, lane, B53_SERDES_MII_REG(MII_BMCR),

			 SERDES_MII_BLK, reg);

}

EXPORT_SYMBOL(b53_serdes_an_restart);



int b53_serdes_link_state(struct b53_device *dev, int port,

			  struct phylink_link_state *state)

{

	u8 lane = b53_serdes_map_lane(dev, port);

	u16 dig, bmcr, bmsr;



	if (lane == B53_INVALID_LANE)

		return 1;



	dig = b53_serdes_read(dev, lane, B53_SERDES_DIGITAL_STATUS,

			      SERDES_DIGITAL_BLK);

	bmcr = b53_serdes_read(dev, lane, B53_SERDES_MII_REG(MII_BMCR),

			       SERDES_MII_BLK);

	bmsr = b53_serdes_read(dev, lane, B53_SERDES_MII_REG(MII_BMSR),

			       SERDES_MII_BLK);



	switch ((dig >> SPEED_STATUS_SHIFT) & SPEED_STATUS_MASK) {

	case SPEED_STATUS_10:

		state->speed = SPEED_10;

		break;

	case SPEED_STATUS_100:

		state->speed = SPEED_100;

		break;

	case SPEED_STATUS_1000:

		state->speed = SPEED_1000;

		break;

	default:

	case SPEED_STATUS_2500:

		state->speed = SPEED_2500;

		break;

	}



	state->duplex = dig & DUPLEX_STATUS ? DUPLEX_FULL : DUPLEX_HALF;

	state->an_enabled = !!(bmcr & BMCR_ANENABLE);

	state->an_complete = !!(bmsr & BMSR_ANEGCOMPLETE);

	state->link = !!(dig & LINK_STATUS);

	if (dig & PAUSE_RESOLUTION_RX_SIDE)

		state->pause |= MLO_PAUSE_RX;

	if (dig & PAUSE_RESOLUTION_TX_SIDE)

		state->pause |= MLO_PAUSE_TX;



	return 0;

}

EXPORT_SYMBOL(b53_serdes_link_state);



void b53_serdes_link_set(struct b53_device *dev, int port, unsigned int mode,

			 phy_interface_t interface, bool link_up)

{

	u8 lane = b53_serdes_map_lane(dev, port);

	u16 reg;



	if (lane == B53_INVALID_LANE)

		return;



	reg = b53_serdes_read(dev, lane, B53_SERDES_MII_REG(MII_BMCR),

			      SERDES_MII_BLK);

	if (link_up)

		reg &= ~BMCR_PDOWN;

	else

		reg |= BMCR_PDOWN;

	b53_serdes_write(dev, lane, B53_SERDES_MII_REG(MII_BMCR),

			 SERDES_MII_BLK, reg);

}

EXPORT_SYMBOL(b53_serdes_link_set);



void b53_serdes_phylink_validate(struct b53_device *dev, int port,

				 unsigned long *supported,

				 struct phylink_link_state *state)

{

	u8 lane = b53_serdes_map_lane(dev, port);



	if (lane == B53_INVALID_LANE)

		return;



	switch (lane) {

	case 0:

		phylink_set(supported, 2500baseX_Full);

		/* fallthrough */

	case 1:

		phylink_set(supported, 1000baseX_Full);

		break;

	default:

		break;

	}

}

EXPORT_SYMBOL(b53_serdes_phylink_validate);



int b53_serdes_init(struct b53_device *dev, int port)

{

	u8 lane = b53_serdes_map_lane(dev, port);

	u16 id0, msb, lsb;



	if (lane == B53_INVALID_LANE)

		return -EINVAL;



	id0 = b53_serdes_read(dev, lane, B53_SERDES_ID0, SERDES_ID0);

	msb = b53_serdes_read(dev, lane, B53_SERDES_MII_REG(MII_PHYSID1),

			      SERDES_MII_BLK);

	lsb = b53_serdes_read(dev, lane, B53_SERDES_MII_REG(MII_PHYSID2),

			      SERDES_MII_BLK);

	if (id0 == 0 || id0 == 0xffff) {

		dev_err(dev->dev, "SerDes not initialized, check settings\n");

		return -ENODEV;

	}



	dev_info(dev->dev,

		 "SerDes lane %d, model: %d, rev %c%d (OUI: 0x%08x)\n",

		 lane, id0 & SERDES_ID0_MODEL_MASK,

		 (id0 >> SERDES_ID0_REV_LETTER_SHIFT) + 0x41,

		 (id0 >> SERDES_ID0_REV_NUM_SHIFT) & SERDES_ID0_REV_NUM_MASK,

		 (u32)msb << 16 | lsb);



	return 0;

}

EXPORT_SYMBOL(b53_serdes_init);



MODULE_AUTHOR("Florian Fainelli <f.fainelli@gmail.com>");

MODULE_DESCRIPTION("B53 Switch SerDes driver");

MODULE_LICENSE("Dual BSD/GPL");

CRA Git | Maintained and supported by SUSTech CRA and CCSE