Commit 1fc870c7 authored Aug 04, 2014 by Olav Haugan Committed by Will Deacon Sep 01, 2014

iommu/arm-smmu: fix programming of SMMU_CBn_TCR for stage 1



Stage-1 context banks do not have the SMMU_CBn_TCR[SL0] field since it
is only applicable to stage-2 context banks.

This patch ensures that we don't set the reserved TCR bits for stage-1
translations.

Cc: <stable@vger.kernel.org>
Signed-off-by: Olav Haugan <ohaugan@codeaurora.org>
Signed-off-by: Will Deacon <will.deacon@arm.com>

parent a18037b2

drivers/iommu/arm-smmu.c

+5 −2

Original line number	Diff line number	Diff line
		@@ -843,8 +843,11 @@ static void arm_smmu_init_context_bank(struct arm_smmu_domain *smmu_domain)
		reg \|= TTBCR_EAE \|
		(TTBCR_SH_IS << TTBCR_SH0_SHIFT) \|
		(TTBCR_RGN_WBWA << TTBCR_ORGN0_SHIFT) \|
		(TTBCR_RGN_WBWA << TTBCR_IRGN0_SHIFT) \|
		(TTBCR_SL0_LVL_1 << TTBCR_SL0_SHIFT);
		(TTBCR_RGN_WBWA << TTBCR_IRGN0_SHIFT);

		if (!stage1)
		reg \|= (TTBCR_SL0_LVL_1 << TTBCR_SL0_SHIFT);

		writel_relaxed(reg, cb_base + ARM_SMMU_CB_TTBCR);

		/* MAIR0 (stage-1 only) */

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